* [d-kernel] [PATCH 0/6] un-def/6.1: update config-aarch64, add Firefly Station P2 support
@ 2023-02-06 4:03 antohami
2023-02-06 4:03 ` [d-kernel] [PATCH 1/6] config-aarch64: enable ARM SCMI PROTOCOL antohami
` (6 more replies)
0 siblings, 7 replies; 8+ messages in thread
From: antohami @ 2023-02-06 4:03 UTC (permalink / raw)
To: devel-kernel
From: Anton Midyukov <antohami@altlinux.org>
Anton Midyukov (6):
config-aarch64: enable ARM SCMI PROTOCOL
config-aarch64: CONFIG_AHCI_DWC=m for enable SATA on Rockchip RK3568
config-aarch64: CONFIG_NVMEM_U_BOOT_ENV=m
config-aarch64: CONFIG_DRM_DW_HDMI_GP_AUDIO=m
config-aarch64: CONFIG_SPI_ROCKCHIP_SFC=m
Add rk3568-firefly-roc-pc.dts from Armbian
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../dts/rockchip/rk3568-firefly-roc-pc.dts | 1044 +++++++++++++++++
config-aarch64 | 23 +-
3 files changed, 1067 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-firefly-roc-pc.dts
--
2.33.6
^ permalink raw reply [flat|nested] 8+ messages in thread
* [d-kernel] [PATCH 1/6] config-aarch64: enable ARM SCMI PROTOCOL
2023-02-06 4:03 [d-kernel] [PATCH 0/6] un-def/6.1: update config-aarch64, add Firefly Station P2 support antohami
@ 2023-02-06 4:03 ` antohami
2023-02-06 4:03 ` [d-kernel] [PATCH 2/6] config-aarch64: CONFIG_AHCI_DWC=m for enable SATA on Rockchip RK3568 antohami
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: antohami @ 2023-02-06 4:03 UTC (permalink / raw)
To: devel-kernel
From: Anton Midyukov <antohami@altlinux.org>
The System Control and Management Interface (SCMI) specification
describes a set of standard interfaces for power, performance and
system management. SCMI is extensible and provides interfaces to
access functions which are often implemented in firmware in the
System Control Processor (SCP).
Link: https://developer.arm.com/Architectures/System%20Control%20and%20Management%20Interface
Signed-off-by: Anton Midyukov <antohami@altlinux.org>
---
config-aarch64 | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/config-aarch64 b/config-aarch64
index 1875cd0920c24..00c4483ffcf77 100644
--- a/config-aarch64
+++ b/config-aarch64
@@ -145,7 +145,19 @@ CONFIG_ARM_RASPBERRYPI_CPUFREQ=m
CONFIG_ARM_TEGRA124_CPUFREQ=m
CONFIG_ARM_TEGRA186_CPUFREQ=m
# CONFIG_QORIQ_CPUFREQ is not set
-# CONFIG_ARM_SCMI_PROTOCOL is not set
+CONFIG_ARM_SCMI_PROTOCOL=y
+CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
+CONFIG_ARM_SCMI_HAVE_SHMEM=y
+CONFIG_ARM_SCMI_HAVE_MSG=y
+CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y
+CONFIG_ARM_SCMI_TRANSPORT_VIRTIO=y
+CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_VERSION1_COMPLIANCE=y
+CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE=y
+CONFIG_ARM_SCMI_POWER_DOMAIN=m
+CONFIG_ARM_SCMI_POWER_CONTROL=m
+CONFIG_ARM_SCMI_CPUFREQ=m
CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_ARM_SCPI_POWER_DOMAIN=y
# CONFIG_ARM_SDE_INTERFACE is not set
@@ -437,6 +449,7 @@ CONFIG_I2C_THUNDERX=m
CONFIG_I2C_XLP9XX=m
CONFIG_I2C_XGENE_SLIMPRO=m
CONFIG_I2C_SLAVE_EEPROM=m
+CONFIG_I2C_SCMI=m
CONFIG_SPI_ARMADA_3700=m
CONFIG_SPI_BCM2835=m
CONFIG_SPI_BCM2835AUX=m
@@ -585,6 +598,7 @@ CONFIG_BATTERY_BQ27XXX_HDQ=m
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
CONFIG_CHARGER_QCOM_SMBB=m
# CONFIG_CHARGER_UCS1002 is not set
+CONFIG_SENSORS_ARM_SCMI=m
CONFIG_SENSORS_ARM_SCPI=m
CONFIG_SENSORS_BT1_PVT=m
CONFIG_TP_BMC=y
@@ -666,6 +680,7 @@ CONFIG_REGULATOR_HI655X=m
# CONFIG_REGULATOR_MCP16502 is not set
CONFIG_REGULATOR_QCOM_SPMI=m
CONFIG_REGULATOR_RK808=y
+CONFIG_REGULATOR_ARM_SCMI=m
# CONFIG_REGULATOR_SY8106A is not set
# CONFIG_REGULATOR_SY8824X is not set
# CONFIG_REGULATOR_VCTRL is not set
@@ -1129,6 +1144,7 @@ CONFIG_CLK_VEXPRESS_OSC=y
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_HI655X=m
CONFIG_COMMON_CLK_SCPI=y
+CONFIG_COMMON_CLK_SCMI=y
# CONFIG_COMMON_CLK_SI514 is not set
# CONFIG_COMMON_CLK_SI570 is not set
# CONFIG_COMMON_CLK_CDCE925 is not set
@@ -1417,6 +1433,7 @@ CONFIG_RESET_RASPBERRYPI=y
# CONFIG_RESET_QCOM_PDC is not set
CONFIG_RESET_SIMPLE=y
CONFIG_RESET_SUNXI=y
+CONFIG_RESET_SCMI=y
CONFIG_COMMON_RESET_HI3660=y
CONFIG_COMMON_RESET_HI6220=y
CONFIG_RESET_TEGRA_BPMP=y
--
2.33.6
^ permalink raw reply [flat|nested] 8+ messages in thread
* [d-kernel] [PATCH 2/6] config-aarch64: CONFIG_AHCI_DWC=m for enable SATA on Rockchip RK3568
2023-02-06 4:03 [d-kernel] [PATCH 0/6] un-def/6.1: update config-aarch64, add Firefly Station P2 support antohami
2023-02-06 4:03 ` [d-kernel] [PATCH 1/6] config-aarch64: enable ARM SCMI PROTOCOL antohami
@ 2023-02-06 4:03 ` antohami
2023-02-06 4:03 ` [d-kernel] [PATCH 3/6] config-aarch64: CONFIG_NVMEM_U_BOOT_ENV=m antohami
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: antohami @ 2023-02-06 4:03 UTC (permalink / raw)
To: devel-kernel
From: Anton Midyukov <antohami@altlinux.org>
Signed-off-by: Anton Midyukov <antohami@altlinux.org>
---
config-aarch64 | 1 +
1 file changed, 1 insertion(+)
diff --git a/config-aarch64 b/config-aarch64
index 00c4483ffcf77..d4e5ecaf4240c 100644
--- a/config-aarch64
+++ b/config-aarch64
@@ -312,6 +312,7 @@ CONFIG_AHCI_SUNXI=m
CONFIG_AHCI_TEGRA=m
CONFIG_AHCI_XGENE=m
CONFIG_AHCI_QORIQ=m
+CONFIG_AHCI_DWC=m
# CONFIG_SATA_AHCI_SEATTLE is not set
# CONFIG_PATA_OF_PLATFORM is not set
# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set
--
2.33.6
^ permalink raw reply [flat|nested] 8+ messages in thread
* [d-kernel] [PATCH 3/6] config-aarch64: CONFIG_NVMEM_U_BOOT_ENV=m
2023-02-06 4:03 [d-kernel] [PATCH 0/6] un-def/6.1: update config-aarch64, add Firefly Station P2 support antohami
2023-02-06 4:03 ` [d-kernel] [PATCH 1/6] config-aarch64: enable ARM SCMI PROTOCOL antohami
2023-02-06 4:03 ` [d-kernel] [PATCH 2/6] config-aarch64: CONFIG_AHCI_DWC=m for enable SATA on Rockchip RK3568 antohami
@ 2023-02-06 4:03 ` antohami
2023-02-06 4:03 ` [d-kernel] [PATCH 4/6] config-aarch64: CONFIG_DRM_DW_HDMI_GP_AUDIO=m antohami
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: antohami @ 2023-02-06 4:03 UTC (permalink / raw)
To: devel-kernel
From: Anton Midyukov <antohami@altlinux.org>
U-Boot stores its setup as environment variables.
This driver adds support for verifying & exporting such data.
It also exposes variables as NVMEM cells so they can be referenced
by other drivers.
Signed-off-by: Anton Midyukov <antohami@altlinux.org>
---
config-aarch64 | 1 +
1 file changed, 1 insertion(+)
diff --git a/config-aarch64 b/config-aarch64
index d4e5ecaf4240c..538e30a99213c 100644
--- a/config-aarch64
+++ b/config-aarch64
@@ -1506,6 +1506,7 @@ CONFIG_NVMEM_ROCKCHIP_OTP=m
CONFIG_NVMEM_ROCKCHIP_EFUSE=m
CONFIG_NVMEM_SUNXI_SID=m
CONFIG_NVMEM_MESON_EFUSE=m
+CONFIG_NVMEM_U_BOOT_ENV=m
# CONFIG_MESON_MX_EFUSE is not set
# CONFIG_FSI is not set
# CONFIG_TEE is not set
--
2.33.6
^ permalink raw reply [flat|nested] 8+ messages in thread
* [d-kernel] [PATCH 4/6] config-aarch64: CONFIG_DRM_DW_HDMI_GP_AUDIO=m
2023-02-06 4:03 [d-kernel] [PATCH 0/6] un-def/6.1: update config-aarch64, add Firefly Station P2 support antohami
` (2 preceding siblings ...)
2023-02-06 4:03 ` [d-kernel] [PATCH 3/6] config-aarch64: CONFIG_NVMEM_U_BOOT_ENV=m antohami
@ 2023-02-06 4:03 ` antohami
2023-02-06 4:03 ` [d-kernel] [PATCH 5/6] config-aarch64: CONFIG_SPI_ROCKCHIP_SFC=m antohami
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: antohami @ 2023-02-06 4:03 UTC (permalink / raw)
To: devel-kernel
From: Anton Midyukov <antohami@altlinux.org>
Support the GP Audio interface which is part of the Synopsys Designware
HDMI block.
Signed-off-by: Anton Midyukov <antohami@altlinux.org>
---
config-aarch64 | 1 +
1 file changed, 1 insertion(+)
diff --git a/config-aarch64 b/config-aarch64
index 538e30a99213c..b237fb7a582c3 100644
--- a/config-aarch64
+++ b/config-aarch64
@@ -830,6 +830,7 @@ CONFIG_DRM_DW_HDMI=m
CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
CONFIG_DRM_DW_HDMI_CEC=m
+CONFIG_DRM_DW_HDMI_GP_AUDIO=m
CONFIG_DRM_DW_MIPI_DSI=m
CONFIG_DRM_VC4=m
CONFIG_DRM_VC4_HDMI_CEC=y
--
2.33.6
^ permalink raw reply [flat|nested] 8+ messages in thread
* [d-kernel] [PATCH 5/6] config-aarch64: CONFIG_SPI_ROCKCHIP_SFC=m
2023-02-06 4:03 [d-kernel] [PATCH 0/6] un-def/6.1: update config-aarch64, add Firefly Station P2 support antohami
` (3 preceding siblings ...)
2023-02-06 4:03 ` [d-kernel] [PATCH 4/6] config-aarch64: CONFIG_DRM_DW_HDMI_GP_AUDIO=m antohami
@ 2023-02-06 4:03 ` antohami
2023-02-06 4:03 ` [d-kernel] [PATCH 6/6] Add rk3568-firefly-roc-pc.dts from Armbian antohami
2023-02-06 7:09 ` [d-kernel] [PATCH 0/6] un-def/6.1: update config-aarch64, add Firefly Station P2 support Vitaly Chikunov
6 siblings, 0 replies; 8+ messages in thread
From: antohami @ 2023-02-06 4:03 UTC (permalink / raw)
To: devel-kernel
From: Anton Midyukov <antohami@altlinux.org>
This enables support for Rockchip serial flash controller.
Signed-off-by: Anton Midyukov <antohami@altlinux.org>
---
config-aarch64 | 1 +
1 file changed, 1 insertion(+)
diff --git a/config-aarch64 b/config-aarch64
index b237fb7a582c3..001d2b521203f 100644
--- a/config-aarch64
+++ b/config-aarch64
@@ -461,6 +461,7 @@ CONFIG_SPI_MESON_SPIFC=y
CONFIG_SPI_ORION=y
CONFIG_SPI_PL022=y
CONFIG_SPI_ROCKCHIP=y
+CONFIG_SPI_ROCKCHIP_SFC=m
# CONFIG_SPI_QCOM_QSPI is not set
CONFIG_SPI_QUP=y
CONFIG_SPI_S3C64XX=y
--
2.33.6
^ permalink raw reply [flat|nested] 8+ messages in thread
* [d-kernel] [PATCH 6/6] Add rk3568-firefly-roc-pc.dts from Armbian
2023-02-06 4:03 [d-kernel] [PATCH 0/6] un-def/6.1: update config-aarch64, add Firefly Station P2 support antohami
` (4 preceding siblings ...)
2023-02-06 4:03 ` [d-kernel] [PATCH 5/6] config-aarch64: CONFIG_SPI_ROCKCHIP_SFC=m antohami
@ 2023-02-06 4:03 ` antohami
2023-02-06 7:09 ` [d-kernel] [PATCH 0/6] un-def/6.1: update config-aarch64, add Firefly Station P2 support Vitaly Chikunov
6 siblings, 0 replies; 8+ messages in thread
From: antohami @ 2023-02-06 4:03 UTC (permalink / raw)
To: devel-kernel
From: Anton Midyukov <antohami@altlinux.org>
Changes have been made to the original patch:
- assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>;
+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
- assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>;
+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
- clocks = <&cru I2S1_MCLKOUT>;
+ clocks = <&cru I2S1_MCLKOUT_TX>;
Link: https://github.com/150balbes/build/blob/armbian-tv/patch/kernel/media-current/00170-v95-rk3568-firefly-roc-pc.patch
Signed-off-by: Anton Midyukov <antohami@altlinux.org>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../dts/rockchip/rk3568-firefly-roc-pc.dts | 1044 +++++++++++++++++
2 files changed, 1045 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-firefly-roc-pc.dts
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 8c15593c0ca4a..0af286891333c 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -72,3 +72,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-firefly-roc-pc.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-firefly-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3568-firefly-roc-pc.dts
new file mode 100644
index 0000000000000..7a8d0e550f239
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-firefly-roc-pc.dts
@@ -0,0 +1,1044 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+ model = "Firefly rk3568-roc-pc";
+ compatible = "firefly,rk3568-roc-pc", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ mmc2 = &sdmmc1;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ fan: gpio_fan {
+ compatible = "gpio-fan";
+ gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+ gpio-fan,speed-map = <0 0
+ 4500 1>;
+ #cooling-cells = <2>;
+ };
+
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ vcc2v5_sys: vcc2v5-ddr {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc2v5-sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc3v3_vga: vcc3v3-vga {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_vga";
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ pcie30_avdd0v9: pcie30-avdd0v9 {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ pcie30_avdd1v8: pcie30-avdd1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ pcie30_3v3: gpio-regulator {
+ compatible = "regulator-gpio";
+ regulator-name = "pcie30_3v3";
+ regulator-min-microvolt = <100000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0x1>;
+ states = <100000 0x0
+ 3300000 0x1>;
+ };
+
+ vcc3v3_bu: vcc3v3-bu {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_bu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_sys: vcc5v0_sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc3v3_lcd0_n: vcc3v3-lcd0-n {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_lcd0_n";
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_lcd1_n: vcc3v3-lcd1-n {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_lcd1_n";
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ };
+
+ vcc5v0_otg: vcc5v0-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_otg_en>;
+ regulator-name = "vcc5v0_otg";
+ };
+
+ vcc3v3_lcd0_n: vcc3v3-lcd0-n {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_lcd0_n";
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_lcd1_n: vcc3v3-lcd1-n {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_lcd1_n";
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_hub_power: vcc-hub-power-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc_hub_power_en>;
+ regulator-name = "vcc_hub_power_en";
+ regulator-always-on;
+ };
+
+ vcc_hub_reset: vcc-hub-reset-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc_hub_reset_en>;
+ regulator-name = "vcc_hub_reset_en";
+ regulator-always-on;
+ };
+
+ pcie_pi6c_oe: pcie-pi6c-oe-regulator {
+ compatible = "regulator-fixed";
+ //enable-active-high;
+ gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pi6c_oe_en>;
+ regulator-name = "pcie_pi6c_oe_en";
+ regulator-always-on;
+ };
+
+ vcc_4g_power: vcc-4g-power-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc_4g_power_en>;
+ regulator-name = "vcc_4g_power_en";
+ regulator-always-on;
+ };
+
+ firefly_leds: leds {
+ compatible = "gpio-leds";
+ power_led: power {
+ label = "firefly:blue:power";
+ linux,default-trigger = "ir-power-click";
+ default-state = "on";
+ gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_power>;
+ };
+
+ user_led: user {
+ label = "firefly:yellow:user";
+ linux,default-trigger = "ir-user-click";
+ default-state = "off";
+ gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_user>;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ status = "okay";
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
+ };
+
+ wireless_wlan: wireless-wlan {
+ compatible = "wlan-platdata";
+ rockchip,grf = <&grf>;
+ wifi_chip_type = "ap6398s";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_host_wake_irq>;
+ WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ wireless_bluetooth: wireless-bluetooth {
+ compatible = "bluetooth-platdata";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ //wifi-bt-power-toggle;
+ uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default", "rts_gpio";
+ pinctrl-0 = <&uart8m0_rtsn>;
+ pinctrl-1 = <&uart8_gpios>;
+ BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
+ BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
+ BT,wake_host_irq = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ flash_led: flash-led {
+ compatible = "led,rgb13h";
+ label = "pwm-flash-led";
+ led-max-microamp = <20000>;
+ flash-max-microamp = <20000>;
+ flash-max-timeout-us = <1000000>;
+ pwms = <&pwm11 0 25000 0>;
+ rockchip,camera-module-index = <1>;
+ rockchip,camera-module-facing = "front";
+ status = "disabled";
+ };
+
+ rk809-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "Analog RK809";
+ simple-audio-card,mclk-fs = <256>;
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&rk809>;
+ };
+ };
+
+ rk_headset: rk-headset {
+ compatible = "rockchip_headset";
+ headset_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_det>;
+ io-channels = <&saradc 2>; //HP_HOOK pin
+ };
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&combphy2 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_thermal {
+ trips {
+ cpu_hot: cpu_hot {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map1 {
+ trip = <&cpu_hot>;
+ cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&gmac0 {
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru SCLK_GMAC0>;
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru SCLK_GMAC0>;
+ assigned-clock-rates = <0>, <125000000>;
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy0>;
+ phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_tx_bus2
+ &gmac0_rx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_rgmii_bus>;
+ tx_delay = <0x3c>;
+ rx_delay = <0x2f>;
+ snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f */
+ snps,reset-delays-us = <0 20000 100000>;
+ status = "okay";
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
+ assigned-clock-rates = <0>, <125000000>;
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_rgmii_bus>;
+ tx_delay = <0x4f>;
+ rx_delay = <0x26>;
+ snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f */
+ snps,reset-delays-us = <0 20000 100000>;
+ status = "okay";
+};
+
+&hdmi {
+ avdd-0v9-supply = <&vdda0v9_image>;
+ avdd-1v8-supply = <&vcca1v8_image>;
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint@0 {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ fusb0: fusb30x@22 {
+ compatible = "fairchild,fusb302";
+ reg = <0x22>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fusb0_int>;
+ int-n-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+ fusb340-switch-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
+ vbus-5v-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ vin-supply = <&vcc5v0_sys>;
+ regulator-compatible = "fan53555-reg";
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1390000>;
+ regulator-ramp-delay = <2300>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-boot-on;
+ regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+ assigned-clock-rates = <12288000>;
+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+ #clock-cells = <1>;
+ clock-names = "mclk";
+ clocks = <&cru I2S1_MCLKOUT_TX>;
+ pinctrl-names = "default", "pmic-sleep",
+ "pmic-power-off", "pmic-reset";
+ pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+
+ rockchip,system-power-controller;
+ #sound-dai-cells = <0>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+ //fb-inner-reg-idxs = <2>;
+ /* 1: rst regs (default in codes), 0: rst the pmic */
+ pmic-reset-func = <0>;
+ /* not save the PMIC_POWER_EN register in uboot */
+ not-save-power-en = <1>;
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vdd_gpu";
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-name = "vdda0v9_image";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vccio_acodec";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcca1v8_image";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+
+ codec {
+ mic-in-differential;
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2s0_8ch {
+ status = "okay";
+};
+
+&i2s1_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1m0_sclktx
+ &i2s1m0_lrcktx
+ &i2s1m0_sdi0
+ &i2s1m0_sdo0>;
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
+};
+
+&mdio0 {
+ rgmii_phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ };
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ };
+};
+
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x2 {
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&pcie30_3v3>;
+
+ status = "okay";
+};
+
+&gic {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&pinctrl {
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wireless-wlan {
+ wifi_host_wake_irq: wifi-host-wake-irq {
+ rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ wireless-bluetooth {
+ uart8_gpios: uart8-gpios {
+ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic_int {
+ rockchip,pins =
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc5v0_otg_en: vcc5v0-otg-en {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc_hub_power_en: vcc-hub-power-en {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc_hub_reset_en: vcc-hub-reset-en {
+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ fusb30x {
+ fusb0_int: fusb0-int {
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ pcie {
+ pcie_pi6c_oe_en: pcie-pi6c-oe-en {
+ rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ 4g {
+ vcc_4g_power_en: vcc-4g-power-en {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ led_power: led-power {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ led_user: led-user {
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ headphone {
+ hp_det: hp-det {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ supports-emmc;
+ non-removable;
+ max-frequency = <200000000>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ max-frequency = <150000000>;
+ supports-sd;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ status = "okay";
+};
+
+&sdmmc2 {
+ max-frequency = <150000000>;
+// max-frequency = <100000000>;
+ supports-sdio;
+ bus-width = <4>;
+ disable-wp;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
+ sd-uhs-sdr104;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ status = "okay";
+};
+
+&sdio_pwrseq {
+ status = "okay";
+ reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <100>;
+};
+
+&wireless_wlan {
+ wifi_chip_type = "ap6275s";
+ status = "okay";
+};
+
+&wireless_bluetooth {
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+// status = "disabled";
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4m1_xfer>;
+ status = "okay";
+};
+
+&uart8 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>;
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ vbus-supply = <&vcc5v0_otg>;
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb2phy1_host {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+//&usbdrd30 {
+// status = "okay";
+//};
+
+//&usbhost30 {
+// status = "okay";
+//};
+
+&rk809 {
+ rtc {
+ status = "disabled";
+ };
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&pwm5 {
+ status = "okay";
+};
+
+&pwm7 {
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};
--
2.33.6
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [d-kernel] [PATCH 0/6] un-def/6.1: update config-aarch64, add Firefly Station P2 support
2023-02-06 4:03 [d-kernel] [PATCH 0/6] un-def/6.1: update config-aarch64, add Firefly Station P2 support antohami
` (5 preceding siblings ...)
2023-02-06 4:03 ` [d-kernel] [PATCH 6/6] Add rk3568-firefly-roc-pc.dts from Armbian antohami
@ 2023-02-06 7:09 ` Vitaly Chikunov
6 siblings, 0 replies; 8+ messages in thread
From: Vitaly Chikunov @ 2023-02-06 7:09 UTC (permalink / raw)
To: ALT Linux kernel packages development
On Mon, Feb 06, 2023 at 11:03:13AM +0700, antohami@basealt.ru wrote:
> From: Anton Midyukov <antohami@altlinux.org>
>
> Anton Midyukov (6):
> config-aarch64: enable ARM SCMI PROTOCOL
> config-aarch64: CONFIG_AHCI_DWC=m for enable SATA on Rockchip RK3568
> config-aarch64: CONFIG_NVMEM_U_BOOT_ENV=m
> config-aarch64: CONFIG_DRM_DW_HDMI_GP_AUDIO=m
> config-aarch64: CONFIG_SPI_ROCKCHIP_SFC=m
> Add rk3568-firefly-roc-pc.dts from Armbian
Applied, thanks.
>
> arch/arm64/boot/dts/rockchip/Makefile | 1 +
> .../dts/rockchip/rk3568-firefly-roc-pc.dts | 1044 +++++++++++++++++
> config-aarch64 | 23 +-
> 3 files changed, 1067 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-firefly-roc-pc.dts
>
> --
> 2.33.6
>
> _______________________________________________
> devel-kernel mailing list
> devel-kernel@lists.altlinux.org
> https://lists.altlinux.org/mailman/listinfo/devel-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2023-02-06 7:09 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-02-06 4:03 [d-kernel] [PATCH 0/6] un-def/6.1: update config-aarch64, add Firefly Station P2 support antohami
2023-02-06 4:03 ` [d-kernel] [PATCH 1/6] config-aarch64: enable ARM SCMI PROTOCOL antohami
2023-02-06 4:03 ` [d-kernel] [PATCH 2/6] config-aarch64: CONFIG_AHCI_DWC=m for enable SATA on Rockchip RK3568 antohami
2023-02-06 4:03 ` [d-kernel] [PATCH 3/6] config-aarch64: CONFIG_NVMEM_U_BOOT_ENV=m antohami
2023-02-06 4:03 ` [d-kernel] [PATCH 4/6] config-aarch64: CONFIG_DRM_DW_HDMI_GP_AUDIO=m antohami
2023-02-06 4:03 ` [d-kernel] [PATCH 5/6] config-aarch64: CONFIG_SPI_ROCKCHIP_SFC=m antohami
2023-02-06 4:03 ` [d-kernel] [PATCH 6/6] Add rk3568-firefly-roc-pc.dts from Armbian antohami
2023-02-06 7:09 ` [d-kernel] [PATCH 0/6] un-def/6.1: update config-aarch64, add Firefly Station P2 support Vitaly Chikunov
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