[devel] [PATCH 27/35] arm64: added Baikal-M SoC and TF307 board device tree

[asheplyakov@yandex.ru]

From: Alexey Sheplyakov <asheplyakov@altlinux.org>

X-feature-Baikal-M
---
 arch/arm64/boot/dts/Makefile                  |    1 +
 arch/arm64/boot/dts/baikal/Makefile           |    9 +
 arch/arm64/boot/dts/baikal/bm-dbm.dts         |  367 ++++++
 arch/arm64/boot/dts/baikal/bm-mbm.dtsi        |  240 ++++
 arch/arm64/boot/dts/baikal/bm-mbm10.dts       |   30 +
 arch/arm64/boot/dts/baikal/bm-mbm20.dts       |  102 ++
 arch/arm64/boot/dts/baikal/bm-qemu.dts        |  163 +++
 arch/arm64/boot/dts/baikal/bm1000-clocks.dtsi |  363 ++++++
 .../arm64/boot/dts/baikal/bm1000-cpufreq.dtsi |  249 ++++
 arch/arm64/boot/dts/baikal/bm1000.dtsi        | 1059 +++++++++++++++++
 10 files changed, 2583 insertions(+)
 create mode 100644 arch/arm64/boot/dts/baikal/Makefile
 create mode 100644 arch/arm64/boot/dts/baikal/bm-dbm.dts
 create mode 100644 arch/arm64/boot/dts/baikal/bm-mbm.dtsi
 create mode 100644 arch/arm64/boot/dts/baikal/bm-mbm10.dts
 create mode 100644 arch/arm64/boot/dts/baikal/bm-mbm20.dts
 create mode 100644 arch/arm64/boot/dts/baikal/bm-qemu.dts
 create mode 100644 arch/arm64/boot/dts/baikal/bm1000-clocks.dtsi
 create mode 100644 arch/arm64/boot/dts/baikal/bm1000-cpufreq.dtsi
 create mode 100644 arch/arm64/boot/dts/baikal/bm1000.dtsi

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 639e01a4d855..2cec7300fef2 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -8,6 +8,7 @@ subdir-y += amlogic
 subdir-y += apm
 subdir-y += apple
 subdir-y += arm
+subdir-y += baikal
 subdir-y += bitmain
 subdir-y += broadcom
 subdir-y += cavium
diff --git a/arch/arm64/boot/dts/baikal/Makefile b/arch/arm64/boot/dts/baikal/Makefile
new file mode 100644
index 000000000000..9729c6e3d4f3
--- /dev/null
+++ b/arch/arm64/boot/dts/baikal/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_BAIKAL) += bm-dbm.dtb
+dtb-$(CONFIG_ARCH_BAIKAL) += bm-mbm10.dtb
+dtb-$(CONFIG_ARCH_BAIKAL) += bm-mbm20.dtb
+dtb-$(CONFIG_ARCH_BAIKAL) += bm-qemu.dtb
+
+always		:= $(dtb-y)
+subdir-y	:= $(dts-dirs)
+clean-files	:= *.dtb
diff --git a/arch/arm64/boot/dts/baikal/bm-dbm.dts b/arch/arm64/boot/dts/baikal/bm-dbm.dts
new file mode 100644
index 000000000000..5a180bfda8be
--- /dev/null
+++ b/arch/arm64/boot/dts/baikal/bm-dbm.dts
@@ -0,0 +1,367 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device tree source for Baikal Electronics DBM board
+ * Copyright (C) 2019-2021 Baikal Electronics, JSC
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "bm1000.dtsi"
+
+/ {
+	model = "Baikal Electronics DBM";
+	compatible = "baikal,baikal-m";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen { };
+
+	panel {
+		compatible = "panel-lvds";
+		width-mm = <223>;
+		height-mm = <125>;
+		data-mapping = "vesa-24";
+		panel-timing {
+			/* 1920x1080 @ 60 Hz */
+			clock-frequency = <148500000>;
+			hactive = <1920>;
+			vactive = <1080>;
+			hsync-len = <44>;
+			hfront-porch = <88>;
+			hback-porch = <148>;
+			vsync-len = <5>;
+			vfront-porch = <4>;
+			vback-porch = <36>;
+		};
+		port {
+			panel0_lvds0: endpoint@0 {
+				remote-endpoint = <&vdu_lvds0_pads>;
+			};
+			panel0_lvds1: endpoint@1 {
+				remote-endpoint = <&vdu_lvds1_pads>;
+			};
+		};
+	};
+
+	buttons-backlight {
+		compatible = "gpio-keys";
+		autorepeat;
+		button-brightness-down {
+			label = "Brightness Down Button";
+			linux,code = <KEY_BRIGHTNESSDOWN>;
+			gpios = <&porta 18 GPIO_ACTIVE_LOW>;
+			debounce-interval = <50>;
+		};
+		button-brightness-up {
+			label = "Brightness Up Button";
+			linux,code = <KEY_BRIGHTNESSUP>;
+			gpios = <&porta 17 GPIO_ACTIVE_LOW>;
+			debounce-interval = <50>;
+		};
+		button-brightness-toggle {
+			label = "Brightness Toggle Button";
+			linux,code = <KEY_BRIGHTNESS_TOGGLE>;
+			gpios = <&porta 31 GPIO_ACTIVE_LOW>;
+			debounce-interval = <50>;
+		};
+	};
+
+	sound {
+		compatible = "baikal,snd_soc_be";
+		baikal,cpu-dai = <&i2s>;
+		baikal,audio-codec = <&tlv320aic3x>;
+	};
+};
+
+&ddr2 {
+	status = "okay";
+};
+
+&espi0 {
+	cs-gpios = <&porta 28 1>; /* todo: get real gpio */
+	status = "okay";
+
+	/* test device #0 */
+	espi_test0 {
+		compatible = "rohm,dh2228fv"; /* same as spidev */
+		reg = <0>;
+		spi-max-frequency = <12000000>;
+		status = "okay";
+	};
+};
+
+&gmac0 {
+	status = "okay";
+	snps,reset-gp-out;
+	snps,reset-active-low;
+};
+
+&gmac1 {
+	status = "okay";
+	snps,reset-gp-out;
+	snps,reset-active-low;
+};
+
+&gpio {
+	status = "okay";
+};
+
+&gpu {
+	system-coherency = <0>;
+};
+
+&hda {
+	status = "okay";
+};
+
+&hdmi {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	tlv320aic3x: tlv320aic3x@18 {
+		#sound-dai-cells = <0>;
+		compatible = "ti,tlv320aic3x";
+		reg = <0x18>;
+		reset-gpios = <&porta 4 GPIO_ACTIVE_LOW>;
+		status = "okay";
+		ai3x-micbias-vg = <1>;
+		ai3x-ocmv = <1>;
+	};
+
+	rtc@56 {
+		compatible = "abracon,abeoz9";
+		reg = <0x56>;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2s {
+	status = "okay";
+	sound-dai = <&tlv320aic3x>;
+	system-clock-frequency = <12000000>;
+};
+
+&mmc0 {
+	status = "okay";
+#if 0
+	/* emmc */
+	non-removable;
+	bus-width = <8>;
+	max-clock = <200000000>;
+#else
+	/* sd */
+	disable-wp;
+	bus-width = <4>;
+	max-clock = <25000000>;
+#endif
+};
+
+&pcie0 {
+	status = "okay";
+};
+
+&pcie1 {
+	status = "okay";
+};
+
+&pcie2 {
+	status = "okay";
+};
+
+&pcie_lcru {
+	status = "okay";
+};
+
+&pvt0 {
+	status = "okay";
+};
+
+&pvt1 {
+	status = "okay";
+};
+
+&pvt2 {
+	status = "okay";
+};
+
+&pvt3 {
+	status = "okay";
+};
+
+&pvt_mali {
+	status = "okay";
+};
+
+&sata0 {
+	status = "okay";
+};
+
+&sata1 {
+	status = "okay";
+};
+
+&smbus0 {
+	status = "okay";
+};
+
+&smbus1 {
+	status = "okay";
+};
+
+&spi0 {
+	num-cs = <4>;
+	cs-gpios =
+		<&porta 24 1>, /* ss0 xp8 - DD53 normal flash */
+		<&porta 25 1>, /* ss1 xp9 */
+		<&porta 26 1>, /* ss2 xp10 */
+		<&porta 27 1>; /* ss3 xp11 */
+	status = "okay";
+
+	/* SPI flash chip #1 */
+	flash0: m25p80@0 {
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <12500000>;
+		status = "okay";
+
+		/* Flash chip0 partitions */
+		mtd0@0 {
+			label = "bl1";
+			reg = <0x00000000 0x00040000>;
+			read-only;
+		};
+
+		mtd1@40000 {
+			label = "fip";
+			reg = <0x00040000 0x007c0000>;
+		};
+
+		mtd2@800000 {
+			label = "rescue";
+			reg = <0x00800000 0x01800000>;
+		};
+	};
+};
+
+#if 0
+/* undefined */
+&spi1 {
+	num-cs = <4>;
+	cs-gpios =
+		<&porta 20 1>, /* ss0 xp15 - DD57 boot flash */
+		<&porta 21 1>, /* ss1 xp16 */
+		<&porta 22 1>, /* ss2 xp17 */
+		<&porta 23 1>; /* ss3 xp18 */
+	status = "okay";
+
+	/* SPI flash chip #2 */
+	flash0: m25p80@0 {
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <12500000>;
+		status = "okay";
+
+		/* Flash chip1 partitions */
+		mtd0@0 {
+			label = "fip_backup";
+			reg = <0x00000000 0x00400000>;
+			read-only;
+		};
+
+		mtd1@400000 {
+			label = "env_backup";
+			reg = <0x00400000 0x00100000>;
+			read-only;
+		};
+
+		mtd2@500000 {
+			label = "data1";
+			reg = <0x00500000 0x01b00000>;
+		};
+	};
+};
+#endif
+
+&timer1 {
+	status = "okay";
+};
+
+&timer2 {
+	status = "okay";
+};
+
+&timer3 {
+	status = "okay";
+};
+
+&timer4 {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
+
+&usb3 {
+	status = "okay";
+};
+
+&vdec {
+	status = "okay";
+};
+
+&vdu0 {
+	status = "okay";
+	enable-gpios = <&porta 16 GPIO_ACTIVE_LOW>;
+	backlight {
+		min-brightness-level = <10>;
+		default-brightness-level = <60>;
+		brightness-level-step = <2>;
+		pwm-frequency = <20000>;
+	};
+	port {
+		vdu_lvds0_pads: endpoint@0 {
+			remote-endpoint = <&panel0_lvds0>;
+		};
+		vdu_lvds1_pads: endpoint@1 {
+			remote-endpoint = <&panel0_lvds1>;
+		};
+		/*vdu_lvds2_pads: endpoint@2 {
+			remote-endpoint = <&panel0_lvds2>;
+		};
+		vdu_lvds3_pads: endpoint@3 {
+			remote-endpoint = <&panel0_lvds3>;
+		};*/
+	};
+};
+
+&vdu1 {
+	status = "okay";
+};
+
+&xgmac0 {
+	status = "okay";
+};
+
+&xgmac1 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/baikal/bm-mbm.dtsi b/arch/arm64/boot/dts/baikal/bm-mbm.dtsi
new file mode 100644
index 000000000000..3603db2a465b
--- /dev/null
+++ b/arch/arm64/boot/dts/baikal/bm-mbm.dtsi
@@ -0,0 +1,240 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device tree include file for MBM-compatible boards
+ * Copyright (C) 2021 Baikal Electronics, JSC
+ */
+
+#include "bm1000.dtsi"
+
+/ {
+	model = "Baikal Electronics MBM";
+	compatible = "baikal,baikal-m";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen { };
+
+	leds {
+		compatible = "gpio-leds";
+		led0 {
+			gpios = <&porta 8 GPIO_ACTIVE_HIGH>;
+			default-state = "keep";
+		};
+	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "MITX-Sound-Card";
+		simple-audio-card,bitclock-master = <&codec0>;
+		simple-audio-card,frame-master = <&codec0>;
+		simple-audio-card,widgets =
+			"Microphone", "Mic Jack",
+			"Headphone", "Headphones",
+			"Speaker", "AUX Out",
+			"Line", "Line In";
+		simple-audio-card,routing =
+			"Headphones", "RHP",
+			"Headphones", "LHP",
+			"AUX Out", "AUXOUT1",
+			"AUX Out", "AUXOUT2",
+			"L2", "Mic Jack",
+			"R2", "Mic Jack",
+			"LAUX", "Line In",
+			"RAUX", "Line In";
+		simple-audio-card,mic-det-gpio = <&porta 26 GPIO_ACTIVE_LOW>;
+		simple-audio-card,format = "i2s";
+		simple-audio-card,cpu {
+			sound-dai = <&i2s>;
+		};
+		codec0: simple-audio-card,codec {
+			sound-dai = <&nau8822 0>;
+		};
+	};
+};
+
+&ddr2 {
+	status = "okay";
+};
+
+&gpio {
+	status = "okay";
+};
+
+&gpu {
+	system-coherency = <0>;
+};
+
+&hdmi {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	bmc@8 {
+		compatible = "tp,mitx2-bmc", "t-platforms,mitx2-bmc";
+		reg = <0x08>;
+	};
+
+	nau8822: nau8822@1a {
+		compatible = "nuvoton,nau8822";
+		#sound-dai-cells = <1>;
+		reg = <0x1a>;
+	};
+
+	gpio@50 {
+		compatible = "nxp,pca9670";
+		#gpio-cells = <2>;
+		gpio-controller;
+		reg = <0x50>;
+	};
+
+	rtc@51 {
+		compatible = "nxp,pcf2129", "nxp,pcf2127";
+		reg = <0x51>;
+	};
+
+	hwmon@52 {
+		compatible = "tp,bm_mitx_hwmon";
+		reg = <0x52>;
+	};
+
+	eeprom@53 {
+		compatible = "atmel,24c32";
+		pagesize = <32>;
+		reg = <0x53>;
+	};
+
+	ps2port@54 {
+		compatible = "tp,tp_serio";
+		reg = <0x54>;
+		interrupt-parent = <&porta>;
+		interrupts = <14 8>;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2s {
+	status = "okay";
+	system-clock-frequency = <12000000>;
+	#sound-dai-cells = <0>;
+};
+
+&mdio0 {
+	status = "disabled";
+};
+
+&mmc0 {
+	status = "okay";
+	disable-wp;
+	bus-width = <4>;
+	max-clock = <25000000>;
+};
+
+&pcie0 {
+	status = "okay";
+	reset-gpios = <&porta 6 GPIO_ACTIVE_LOW>;
+};
+
+&pcie2 {
+	status = "okay";
+	reset-gpios = <&porta 3 GPIO_ACTIVE_LOW>;
+};
+
+&pcie_lcru {
+	status = "okay";
+};
+
+&porta {
+	pcieclk {
+		gpio-hog;
+		gpios = <1 GPIO_ACTIVE_LOW>;
+		output-high;
+		line-name = "pcie-x8-clock";
+	};
+};
+
+&pvt0 {
+	status = "okay";
+};
+
+&pvt1 {
+	status = "okay";
+};
+
+&pvt2 {
+	status = "okay";
+};
+
+&pvt3 {
+	status = "okay";
+};
+
+&pvt_mali {
+	status = "okay";
+};
+
+&sata0 {
+	status = "okay";
+};
+
+&sata1 {
+	status = "okay";
+};
+
+&smbus0 {
+	status = "okay";
+};
+
+&smbus1 {
+	status = "okay";
+};
+
+&spi0 {
+	num-cs = <4>;
+	cs-gpios = <0>;
+	status = "okay";
+};
+
+&timer1 {
+	status = "okay";
+};
+
+&timer2 {
+	status = "okay";
+};
+
+&timer3 {
+	status = "okay";
+};
+
+&timer4 {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
+
+&usb3 {
+	status = "okay";
+};
+
+&vdec {
+	status = "okay";
+};
+
+&vdu1 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/baikal/bm-mbm10.dts b/arch/arm64/boot/dts/baikal/bm-mbm10.dts
new file mode 100644
index 000000000000..8e02d3e08f3e
--- /dev/null
+++ b/arch/arm64/boot/dts/baikal/bm-mbm10.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device tree source for MBM 1.0 compatible boards:
+ *   - TP-TF307-MB-A0 Rev.1.0 (BM1BM1-A)
+ *   - TF307-MB-S-C Rev.3.0
+ *
+ * Copyright (C) 2021 Baikal Electronics, JSC
+ */
+
+/dts-v1/;
+
+#include "bm-mbm.dtsi"
+
+/ {
+	sound {
+		simple-audio-card,hp-det-gpio = <&porta 27 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&gmac0 {
+	status = "okay";
+	snps,reset-gp-out;
+	snps,reset-active-low;
+};
+
+&gmac1 {
+	status = "okay";
+	snps,reset-gp-out;
+	snps,reset-active-low;
+};
diff --git a/arch/arm64/boot/dts/baikal/bm-mbm20.dts b/arch/arm64/boot/dts/baikal/bm-mbm20.dts
new file mode 100644
index 000000000000..1c0a459a2781
--- /dev/null
+++ b/arch/arm64/boot/dts/baikal/bm-mbm20.dts
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device tree source for MBM 2.0 compatible boards:
+ *   - TF307-MB-S-D Rev.4.0 (BM1BM1-D)
+ *
+ * Copyright (C) 2021 Baikal Electronics, JSC
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "bm-mbm.dtsi"
+
+/ {
+	panel {
+		/* In order to utilize LVDS LCD panel, make sure that
+		   status is "okay" along with &vdu0 status (see below). */
+		status = "disabled";
+		compatible = "panel-lvds";
+		width-mm = <223>;
+		height-mm = <125>;
+		data-mapping = "vesa-24";
+		panel-timing {
+			/* 1920x1080 @ 60 Hz */
+			clock-frequency = <148500000>;
+			hactive = <1920>;
+			vactive = <1080>;
+			hsync-len = <44>;
+			hfront-porch = <88>;
+			hback-porch = <148>;
+			vsync-len = <5>;
+			vfront-porch = <4>;
+			vback-porch = <36>;
+		};
+		port {
+			panel0_lvds0: endpoint@0 {
+				remote-endpoint = <&vdu_lvds0_pads>;
+			};
+			panel0_lvds1: endpoint@1 {
+				remote-endpoint = <&vdu_lvds1_pads>;
+			};
+		};
+	};
+
+	buttons-backlight {
+		compatible = "gpio-keys";
+		autorepeat;
+		button-brightness-down {
+			label = "Brightness Down Button";
+			linux,code = <KEY_BRIGHTNESSDOWN>;
+			gpios = <&porta 18 GPIO_ACTIVE_LOW>;
+			debounce-interval = <50>;
+		};
+		button-brightness-up {
+			label = "Brightness Up Button";
+			linux,code = <KEY_BRIGHTNESSUP>;
+			gpios = <&porta 17 GPIO_ACTIVE_LOW>;
+			debounce-interval = <50>;
+		};
+		button-brightness-toggle {
+			label = "Brightness Toggle Button";
+			linux,code = <KEY_BRIGHTNESS_TOGGLE>;
+			gpios = <&porta 31 GPIO_ACTIVE_LOW>;
+			debounce-interval = <50>;
+		};
+	};
+
+	sound {
+		simple-audio-card,hp-det-gpio = <&porta 29 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&gmac0 {
+	status = "okay";
+	snps,reset-gpios = <&porta 19 GPIO_ACTIVE_LOW>;
+};
+
+&gmac1 {
+	status = "okay";
+	snps,reset-gpios = <&porta 20 GPIO_ACTIVE_LOW>;
+};
+
+&vdu0 {
+	/* In order to utilize LVDS LCD panel, make sure that
+	   status is "okay" along with panel status (see above). */
+	status = "disabled";
+	enable-gpios = <&porta 16 GPIO_ACTIVE_LOW>;
+	backlight {
+		min-brightness-level = <10>;
+		default-brightness-level = <60>;
+		brightness-level-step = <2>;
+		pwm-frequency = <20000>;
+	};
+	port {
+		vdu_lvds0_pads: endpoint@0 {
+			remote-endpoint = <&panel0_lvds0>;
+		};
+		vdu_lvds1_pads: endpoint@1 {
+			remote-endpoint = <&panel0_lvds1>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/baikal/bm-qemu.dts b/arch/arm64/boot/dts/baikal/bm-qemu.dts
new file mode 100644
index 000000000000..c6350c0aaeb5
--- /dev/null
+++ b/arch/arm64/boot/dts/baikal/bm-qemu.dts
@@ -0,0 +1,163 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device tree source for Baikal-M software emulator (QEMU) platform
+ * Copyright (C) 2018-2021 Baikal Electronics, JSC
+ */
+
+/dts-v1/;
+
+#include "bm1000.dtsi"
+
+/*
+ * Device "flash@0" was added to allow UEFI to boot on emulator.
+ * TODO: the tree should be replaced by actual Baikal-M component tree
+ */
+
+/ {
+	model = "Baikal Electronics Baikal-M virtual platform";
+	compatible = "baikal,baikal-m";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		bootargs = "root=/dev/ram rw rootwait console=ttyS0,115200n8 earlyprintk=uart8250,mmio32,0x20230000,115200";
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* 16GB */
+		reg = <0x00000000 0x80000000 0x0 0x80000000
+		       0x00000008 0x80000000 0x1 0x80000000>;
+	};
+
+	/* XXX: Temporary fix for qemu to work */
+	/* Device is necessary for UEFI to boot on QEMU, need to replace it with something later */
+	flash@0 {
+		compatible = "cfi-flash";
+		reg = <0x0 0x4000000 0x0 0x4000000>;
+		bank-width = <0x4>;
+	};
+
+	panel: panel {
+		compatible = "auo,b133htn01";		/* 1920x1080 */
+		/*compatible = "auo,b133xtn01;		/* 1366x768 */
+		/*compatible = "auo,b101aw03";		/* 1024x600 */
+		/*compatible = "innolux,g121x1-l03";	/* 1024x768 */
+		/*compatible = "auo,b101ean01";		/* 1280x800 */
+
+		port {
+			lcd_panel: endpoint {
+				remote-endpoint = <&vdu_pads>;
+			};
+		};
+	};
+
+	/*panel_hdmi: panel {
+		compatible = "edt,et057090dhu";
+
+		port {
+			lcd_hdmi_panel: endpoint {
+				remote-endpoint = <&vdu_hdmi_pads>;
+			};
+		};
+	};*/
+};
+
+&gmac0 {
+	status = "okay";
+};
+
+&gmac1 {
+	status = "okay";
+};
+
+&sata0 {
+	status = "okay";
+};
+
+&sata1 {
+	status = "okay";
+};
+
+&spi0 {
+	num-cs = <6>;
+	status = "okay";
+
+	/* SPI flash chip #1 */
+	flash0: m25p80@0 {
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <50000000>;
+		status = "okay";
+
+		/* Flash chip0 partitions */
+		mtd0@0 {
+			label = "fip";
+			reg = <0x00000000 0x00400000>;
+			read-only;
+		};
+
+		mtd1@400000 {
+			label = "env";
+			reg = <0x00400000 0x00100000>;
+		};
+
+		mtd2@500000 {
+			label = "kernel";
+			reg = <0x00500000 0x00400000>;
+		};
+
+		mtd3@900000 {
+			label = "rootfs";
+			reg = <0x00900000 0x00800000>;
+		};
+
+		mtd4@1100000 {
+			label = "data0";
+			reg = <0x01100000 0x00f00000>;
+		};
+	};
+
+	/* SPI flash chip #2 */
+	flash1: m25p80@1 {
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <50000000>;
+		status = "okay";
+
+		/* Flash chip1 partitions */
+		mtd0@0 {
+			label = "fip_backup";
+			reg = <0x00000000 0x00400000>;
+			read-only;
+		};
+
+		mtd1@400000 {
+			label = "env_backup";
+			reg = <0x00400000 0x00100000>;
+			read-only;
+		};
+
+		mtd2@500000 {
+			label = "data1";
+			reg = <0x00500000 0x01b00000>;
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&vdu0 {
+	port {
+		vdu_pads: endpoint {
+			remote-endpoint = <&lcd_panel>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/baikal/bm1000-clocks.dtsi b/arch/arm64/boot/dts/baikal/bm1000-clocks.dtsi
new file mode 100644
index 000000000000..0a5579d3694b
--- /dev/null
+++ b/arch/arm64/boot/dts/baikal/bm1000-clocks.dtsi
@@ -0,0 +1,363 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device tree include file for BE-M1000 SoC clocks
+ * Copyright (C) 2017-2021 Baikal Electronics, JSC
+ */
+
+/ {
+	/* external oscillator */
+	osc25: oscillator25 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+		clock-output-names = "osc25";
+	};
+
+	/* external oscillator */
+	osc27: oscillator27 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <27000000>;
+		clock-output-names = "osc27";
+	};
+
+	cmu_cluster0: cmu_cluster0 {
+		compatible = "baikal,cmu";
+		clock-output-names = "baikal-ca57_cmu0";
+		#clock-cells = <0>;
+		clocks = <&osc25>;
+		cmu-id = <0x28000000>;
+		max = <1500000000>;
+		min = <500000000>;
+		clock-frequency = <1500000000>;
+	};
+
+	cmu_cluster1: cmu_cluster1 {
+		compatible = "baikal,cmu";
+		clock-output-names = "baikal-ca57_cmu1";
+		#clock-cells = <0>;
+		clocks = <&osc25>;
+		cmu-id = <0xc000000>;
+		max = <1500000000>;
+		min = <500000000>;
+		clock-frequency = <1500000000>;
+	};
+
+	cmu_cluster2: cmu_cluster2 {
+		compatible = "baikal,cmu";
+		clock-output-names = "baikal-ca57_cmu2";
+		#clock-cells = <0>;
+		clocks = <&osc25>;
+		cmu-id = <0xa000000>;
+		max = <1500000000>;
+		min = <500000000>;
+		clock-frequency = <1500000000>;
+	};
+
+	cmu_cluster3: cmu_cluster3 {
+		compatible = "baikal,cmu";
+		clock-output-names = "baikal-ca57_cmu3";
+		#clock-cells = <0>;
+		clocks = <&osc25>;
+		cmu-id = <0x26000000>;
+		max = <1500000000>;
+		min = <500000000>;
+		clock-frequency = <1500000000>;
+	};
+
+	cmu0_avlsp: cmu0_avlsp {
+		compatible = "baikal,cmu";
+		#clock-cells = <1>;
+		clock-output-names = "baikal-avlsp_cmu0";
+		clock-names =
+			"gpio",		// <0>
+			"uart1",	// <1>
+			"uart2",	// <2>
+			"apb",		// <3>
+			"spi",		// <4>
+			"espi",		// <5>
+			"i2c1",		// <6>
+			"i2c2",		// <7>
+			"timer1",	// <8>
+			"timer2",	// <9>
+			"timer3",	// <10>
+			"timer4",	// <11>
+			"dmac",		// <12>
+			"smbus1",	// <13>
+			"smbus2",	// <14>
+			"hda_sys_clk",	// <15>
+			"hda_clk48",	// <16>
+			"mshc_axi",	// <17>
+			"mshc_ahb",	// <18>
+			"mshc_tx_x2",	// <19>
+			"mshc_b",	// <20>
+			"mshc_tm",	// <21>
+			"mshc_cqetm",	// <22>
+			"hwa_clu",	// <23>
+			"hwa_clu_hf",	// <24>
+			"hwa_axi",	// <25>
+			"vdu_axi",	// <26>
+			"smmu";		// <27>
+		clock-indices =
+			<0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, <10>,
+			<11>, <12>, <13>, <14>, <15>, <16>, <17>, <18>, <19>,
+			<20>, <21>, <22>, <23>, <24>, <25>, <26>, <27>;
+		clocks = <&osc25>;
+		cmu-id = <0x20000000>;
+		max = <2100000000>;
+		min = <800000>;
+		clock-frequency = <1200000000>;
+	};
+
+	cmu1_avlsp: cmu1_avlsp {
+		compatible = "baikal,cmu";
+		clock-output-names = "baikal-avlsp_cmu1";
+		#clock-cells = <0>;
+		clocks = <&osc27>;
+		cmu-id = <0x20010000>;
+		max = <2100000000>;
+		min = <13500000>;
+		clock-frequency = <1039500000>;
+	};
+
+	cmu_mali: cmu_mali {
+		compatible = "baikal,cmu";
+		clock-output-names = "baikal-mali-cmu";
+		#clock-cells = <0>;
+		clocks = <&osc25>;
+		clock-names = "aclk";
+		cmu-id = <0x2a000000>;
+		max = <800000000>;
+		min = <400000000>;
+		clock-frequency = <750000000>;
+	};
+
+	cmu0_xgbe: cmu0_xgbe {
+		compatible = "baikal,cmu";
+		clock-output-names = "baikal-xgbe-cmu0";
+		#clock-cells = <1>;
+		clocks = <&osc25>;
+		clock-names = "csr50mhz", "gmac0_tx2", "gmac1_tx2", "hdmi_aclk", "isfr";
+		clock-indices = <0>, <10>, <13>, <15>, <17>;
+		cmu-id = <0x30000000>;
+		max = <1250000000>;
+		min = <50000000>;
+		clock-frequency = <1250000000>;
+	};
+
+	cmu1_xgbe: cmu1_xgbe {
+		compatible = "baikal,cmu";
+		clock-output-names = "baikal-xgbe-cmu1";
+		#clock-cells = <1>;
+		clocks = <&osc27>;
+		clock-indices = <0>;
+		clock-names = "pixelclk";
+		cmu-id = <0x30010000>;
+		max = <600000000>;
+		min = <13500000>;
+		clock-frequency = <25250000>;
+	};
+
+	clocks {
+		cpu_clk: cpu_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <1500000000>;
+			clock-output-names = "cpuclk";
+		};
+
+		apb_clk: apb_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+			clock-output-names = "apb_pclk";
+		};
+
+		uart_clk: uart_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <7273800>;
+			clock-output-names = "soc_uartclk";
+		};
+
+		i2c_clk: i2c_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <100000000>;
+			clock-output-names = "soc_i2cclk";
+		};
+
+		smbus_clk: smbus_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+			clock-output-names = "soc_smbusclk";
+		};
+
+		timer1_clk: timer1_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+			clock-output-names = "soc_timer1clk";
+		};
+
+		timer2_clk: timer2_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+			clock-output-names = "soc_timer2clk";
+		};
+
+		timer3_clk: timer3_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+			clock-output-names = "soc_timer3clk";
+		};
+
+		timer4_clk: timer4_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+			clock-output-names = "soc_timer4clk";
+		};
+
+		gpio_clk: gpio_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <1000000>;
+			clock-output-names = "soc_gpioclk";
+		};
+
+		spi_clk: spi_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+			clock-output-names = "soc_spiclk";
+		};
+
+		soc_ethclk: ethclk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+			clock-output-names = "eth_clk";
+		};
+
+		soc_xgbeclk: xgbeclk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <156250000>;
+			clock-output-names = "xgbe_clk";
+		};
+
+		soc_smc50mhz: clk50mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+			clock-output-names = "smc_clk";
+		};
+
+		soc_faxiclk: refclk400mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <400000000>;
+			clock-output-names = "faxi_clk";
+		};
+
+		soc_tmp_clk: refclkXXXmhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <100000000>;
+			clock-output-names = "tmpclk";
+		};
+
+		gpu_clk: gpu_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <750000000>;
+			clock-output-names = "gpuclk";
+		};
+		gpu_opp_table: opp_table_gpu {
+			compatible = "operating-points-v2", "operating-points-v2-mali";
+
+			opp@400000000 {
+				opp-hz = /bits/ 64 <400000000>;
+				clock-latency-ns = <10000000>;
+			};
+			opp@450000000 {
+				opp-hz = /bits/ 64 <450000000>;
+				clock-latency-ns = <10000000>;
+			};
+			opp@500000000 {
+				opp-hz = /bits/ 64 <500000000>;
+				clock-latency-ns = <10000000>;
+			};
+			opp@550000000 {
+				opp-hz = /bits/ 64 <550000000>;
+				clock-latency-ns = <10000000>;
+			};
+			opp@600000000 {
+				opp-hz = /bits/ 64 <600000000>;
+				clock-latency-ns = <10000000>;
+			};
+			opp@650000000 {
+				opp-hz = /bits/ 64 <650000000>;
+				clock-latency-ns = <10000000>;
+			};
+			opp@700000000 {
+				opp-hz = /bits/ 64 <700000000>;
+				clock-latency-ns = <10000000>;
+			};
+			opp@750000000 {
+				opp-hz = /bits/ 64 <750000000>;
+				clock-latency-ns = <10000000>;
+			};
+		};
+
+		clk_ahb: clk_ahb {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <100000000>;
+			clock-output-names = "clk_ahb";
+		};
+
+		clk_xin: clk_xin {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <100000000>;
+			clock-output-names = "clk_xin";
+		};
+
+		cortex_cmu: cmu@cortex {
+			compatible = "baikal,cmu-device-clock";
+			#clock-cells = <1>;
+			clock-frequency = <1000000000>;
+			clock-output-names = "baikal-cmu";
+		};
+
+		avlsp_cmu1: cmu1@avlsp {
+			compatible = "baikal,cmu-device-clock";
+			#clock-cells = <1>;
+			clock-indices = <26>;
+			clock-frequency = <240000000>;
+			clock-output-names = "baikal-cmu";
+		};
+
+		usb_clk: usb_clk@1f04d074 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-names = "usbclk";
+			clock-frequency = <500000000>;
+			clock-output-names = "usbclk";
+		};
+
+		cmu1_avlsp_div7: cmu1_avlsp_div7 {
+			compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock";
+			clocks = <&cmu1_avlsp>;
+			#clock-cells = <0>;
+			clock-div = <7>;
+			clock-mult = <1>;
+			clock-output-names = "lvds_clk";
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/baikal/bm1000-cpufreq.dtsi b/arch/arm64/boot/dts/baikal/bm1000-cpufreq.dtsi
new file mode 100644
index 000000000000..76fee58d8bfc
--- /dev/null
+++ b/arch/arm64/boot/dts/baikal/bm1000-cpufreq.dtsi
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device tree include file for BE-M1000 SoC CPU frequencies
+ * Copyright (C) 2020-2021 Baikal Electronics, JSC
+ */
+
+/ {
+	cpufreq {
+		cluster0_opp: opp_table0 {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp@1500 {
+				opp-hz = /bits/ 64 <1500000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@1400 {
+				opp-hz = /bits/ 64 <1400000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@1300 {
+				opp-hz = /bits/ 64 <1300000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@1200 {
+				opp-hz = /bits/ 64 <1200000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@1100 {
+				opp-hz = /bits/ 64 <1100000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@1000 {
+				opp-hz = /bits/ 64 <1000000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@900 {
+				opp-hz = /bits/ 64 <900000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@800 {
+				opp-hz = /bits/ 64 <800000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@700 {
+				opp-hz = /bits/ 64 <700000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@600 {
+				opp-hz = /bits/ 64 <600000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@500 {
+				opp-hz = /bits/ 64 <500000000>;
+				clock-latency-ns = <10000000>;
+			};
+		};
+
+		cluster1_opp: opp_table1 {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp@1500 {
+				opp-hz = /bits/ 64 <1500000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@1400 {
+				opp-hz = /bits/ 64 <1400000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@1300 {
+				opp-hz = /bits/ 64 <1300000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@1200 {
+				opp-hz = /bits/ 64 <1200000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@1100 {
+				opp-hz = /bits/ 64 <1100000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@1000 {
+				opp-hz = /bits/ 64 <1000000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@900 {
+				opp-hz = /bits/ 64 <900000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@800 {
+				opp-hz = /bits/ 64 <800000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@700 {
+				opp-hz = /bits/ 64 <700000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@600 {
+				opp-hz = /bits/ 64 <600000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@500 {
+				opp-hz = /bits/ 64 <500000000>;
+				clock-latency-ns = <10000000>;
+			};
+		};
+
+		cluster2_opp: opp_table2 {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp@1500 {
+				opp-hz = /bits/ 64 <1500000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@1400 {
+				opp-hz = /bits/ 64 <1400000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@1300 {
+				opp-hz = /bits/ 64 <1300000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@1200 {
+				opp-hz = /bits/ 64 <1200000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@1100 {
+				opp-hz = /bits/ 64 <1100000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@1000 {
+				opp-hz = /bits/ 64 <1000000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@900 {
+				opp-hz = /bits/ 64 <900000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@800 {
+				opp-hz = /bits/ 64 <800000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@700 {
+				opp-hz = /bits/ 64 <700000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@600 {
+				opp-hz = /bits/ 64 <600000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@500 {
+				opp-hz = /bits/ 64 <500000000>;
+				clock-latency-ns = <10000000>;
+			};
+		};
+
+		cluster3_opp: opp_table3 {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp@1500 {
+				opp-hz = /bits/ 64 <1500000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@1400 {
+				opp-hz = /bits/ 64 <1400000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@1300 {
+				opp-hz = /bits/ 64 <1300000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@1200 {
+				opp-hz = /bits/ 64 <1200000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@1100 {
+				opp-hz = /bits/ 64 <1100000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@1000 {
+				opp-hz = /bits/ 64 <1000000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@900 {
+				opp-hz = /bits/ 64 <900000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@800 {
+				opp-hz = /bits/ 64 <800000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@700 {
+				opp-hz = /bits/ 64 <700000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@600 {
+				opp-hz = /bits/ 64 <600000000>;
+				clock-latency-ns = <10000000>;
+			};
+
+			opp@500 {
+				opp-hz = /bits/ 64 <500000000>;
+				clock-latency-ns = <10000000>;
+			};
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/baikal/bm1000.dtsi b/arch/arm64/boot/dts/baikal/bm1000.dtsi
new file mode 100644
index 000000000000..bc69835c4d4f
--- /dev/null
+++ b/arch/arm64/boot/dts/baikal/bm1000.dtsi
@@ -0,0 +1,1059 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device tree include file for BE-M1000 SoC
+ * Copyright (C) 2017-2021 Baikal Electronics, JSC
+ */
+
+#include "bm1000-clocks.dtsi"
+#include "bm1000-cpufreq.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/*
+ * ARM GICv3 bindings assume interrupts (in each range) counting from 0:
+ * PPI: 0..15
+ * SPI: 0..987
+ * Baikal-M documentation ("Interrupt map") places all interrupts into the
+ * linear map: SGI(0..15), PPI(16..31), SPI(32-1019).
+ * So real interrupt IDs in this device tree must be calculated as follows:
+ * PPI_real = PPI_from_documentation - 16
+ * SPI_real = SPI_from_documentation - 32
+ */
+
+/ {
+	compatible = "baikal,arm", "baikal,baikal-m-soc", "simple-bus";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&gic>;
+
+	aliases {
+		ethernet1		= &gmac0;
+		ethernet2		= &gmac1;
+		ethernet3		= &xgmac0;
+		ethernet4		= &xgmac1;
+		gic			= &gic;
+		gpio			= &gpio;
+		hda			= &hda;
+		i2c0			= &i2c0;
+		i2c1			= &i2c1;
+		i2s			= &i2s;
+		memory-controller1	= &ddr1;
+		memory-controller2	= &ddr2;
+		mmc0			= &mmc0;
+		pvt0			= &pvt0;
+		pvt1			= &pvt1;
+		pvt2			= &pvt2;
+		pvt3			= &pvt3;
+		pvt_mali		= &pvt_mali;
+		sata0			= &sata0;
+		sata1			= &sata1;
+		serial0			= &uart0;
+		serial1			= &uart1;
+		smbus0			= &smbus0;
+		smbus1			= &smbus1;
+		spi			= &spi0;
+		ssi0			= &spi0;
+		timer1			= &timer1;
+		timer2			= &timer2;
+		timer3			= &timer3;
+		timer4			= &timer4;
+		usb2			= &usb2;
+		usb3			= &usb3;
+		vdec			= &vdec;
+		vdu_lvds		= &vdu0;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		/* Do not use 'cpu-map'. It leads to wrong topology. */
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a57";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			i-cache-size = <0xc000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			clocks = <&cmu_cluster0>;
+			next-level-cache = <&cluster0_l2>;
+			clock-names = "baikal-ca57_cmu";
+			operating-points-v2 = <&cluster0_opp>;
+		};
+
+		CPU1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a57";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+			i-cache-size = <0xc000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			clocks = <&cmu_cluster0>;
+			next-level-cache = <&cluster0_l2>;
+			clock-names = "baikal-ca57_cmu";
+			operating-points-v2 = <&cluster0_opp>;
+		};
+
+		CPU2: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a57";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			i-cache-size = <0xc000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			clocks = <&cmu_cluster1>;
+			next-level-cache = <&cluster1_l2>;
+			clock-names = "baikal-ca57_cmu";
+			operating-points-v2 = <&cluster1_opp>;
+		};
+
+		CPU3: cpu@101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a57";
+			reg = <0x0 0x101>;
+			enable-method = "psci";
+			i-cache-size = <0xc000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			clocks = <&cmu_cluster1>;
+			next-level-cache = <&cluster1_l2>;
+			clock-names = "baikal-ca57_cmu";
+			operating-points-v2 = <&cluster1_opp>;
+		};
+
+		CPU4: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a57";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+			i-cache-size = <0xc000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			clocks = <&cmu_cluster2>;
+			next-level-cache = <&cluster2_l2>;
+			clock-names = "baikal-ca57_cmu";
+			operating-points-v2 = <&cluster2_opp>;
+		};
+
+		CPU5: cpu@201 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a57";
+			reg = <0x0 0x201>;
+			enable-method = "psci";
+			i-cache-size = <0xc000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			clocks = <&cmu_cluster2>;
+			next-level-cache = <&cluster2_l2>;
+			clock-names = "baikal-ca57_cmu";
+			operating-points-v2 = <&cluster2_opp>;
+		};
+
+		CPU6: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a57";
+			reg = <0x0 0x300>;
+			enable-method = "psci";
+			i-cache-size = <0xc000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			clocks = <&cmu_cluster3>;
+			next-level-cache = <&cluster3_l2>;
+			clock-names = "baikal-ca57_cmu";
+			operating-points-v2 = <&cluster3_opp>;
+		};
+
+		CPU7: cpu@301 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a57";
+			reg = <0x0 0x301>;
+			enable-method = "psci";
+			i-cache-size = <0xc000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			clocks = <&cmu_cluster3>;
+			next-level-cache = <&cluster3_l2>;
+			clock-names = "baikal-ca57_cmu";
+			operating-points-v2 = <&cluster3_opp>;
+		};
+
+		cluster0_l2: l2-cache0 {
+			compatible = "cache";
+			cache-size = <0x100000>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			cache-unified;
+			cache-level = <2>;
+			next-level-cache = <&l3>;
+		};
+
+		cluster1_l2: l2-cache1 {
+			compatible = "cache";
+			cache-size = <0x100000>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			cache-unified;
+			cache-level = <2>;
+			next-level-cache = <&l3>;
+		};
+
+		cluster2_l2: l2-cache2 {
+			compatible = "cache";
+			cache-size = <0x100000>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			cache-unified;
+			cache-level = <2>;
+			next-level-cache = <&l3>;
+		};
+
+		cluster3_l2: l2-cache3 {
+			compatible = "cache";
+			cache-size = <0x100000>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			cache-unified;
+			cache-level = <2>;
+			next-level-cache = <&l3>;
+		};
+
+		l3: l3-cache {
+			cache-size = <0x800000>;
+			cache-unified;
+			cache-level = <3>;
+		};
+	};
+
+	pmu {
+		compatible = "arm,cortex-a57-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* DDR0 (e200000, 10000, SPI_161-166_?) */
+		ddr1: memory-controller1@e200000 {
+			compatible = "be,emc", "be,memory-controller";
+			reg = <0x0 0x0e200000 0x0 0x10000>;
+			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, /* ddr dfi alert err */
+				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, /* ddr ecc corrected err */
+				     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, /* ddr ecc uncorrected err */
+				     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, /* ddr sbr done */
+				     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, /* ddr ecc corrected err fault */
+				     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; /* ddr ecc uncorrected err fault */
+			clocks = <&soc_smc50mhz>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+		};
+
+		/* DDR1 (22200000, 10000, SPI_171-176_?) */
+		ddr2: memory-controller2@22200000 {
+			compatible = "be,emc", "be,memory-controller";
+			reg = <0x0 0x22200000 0x0 0x10000>;
+			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, /* ddr dfi alert err */
+				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, /* ddr ecc corrected err */
+				     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, /* ddr ecc uncorrected err */
+				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* ddr sbr done */
+				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* ddr ecc corrected err fault */
+				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; /* ddr ecc uncorrected err fault */
+			clocks = <&soc_smc50mhz>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+		};
+
+		pcie_lcru: lcru@2000000 {
+			compatible = "syscon";
+			reg = <0x0 0x2000000 0x0 0x80000>;
+			/*big-endian;*/
+			status = "disabled";
+		};
+
+		pcie0: pcie@2200000 { /* PCIe x4 #0 */
+			compatible = "baikal,pcie-m", "snps,dw-pcie";
+			reg = <0x0 0x02200000 0x0 0x1000>,   /* RC config space */
+			      <0x0 0x40100000 0x0 0x100000>; /* PCI config space */
+			reg-names = "dbi", "config";
+			interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, /* AER */
+				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; /* MSI */
+			#interrupt-cells = <1>;
+			baikal,pcie-lcru = <&pcie_lcru 0>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			ranges = <0x81000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,   /* I/O */
+				 <0x82000000 0x0 0x40000000 0x4 0x00000000 0x0 0x40000000>; /* 32b non-prefetchable memory */
+			msi-parent = <&its 0x0>;
+			msi-map = <0x0 &its 0x0 0x10000>;
+			num-lanes = <4>;
+			num-viewport = <4>;
+			bus-range = <0x0 0xff>;
+			status = "disabled";
+		};
+
+		pcie1: pcie@2210000 { /* PCIe x4 #1 */
+			compatible = "baikal,pcie-m", "snps,dw-pcie";
+			reg = <0x0 0x02210000 0x0 0x1000>,   /* RC config space */
+			      <0x0 0x50100000 0x0 0x100000>; /* PCI config space */
+			reg-names = "dbi", "config";
+			interrupts = <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,	/* AER */
+				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;	/* MSI */
+			#interrupt-cells = <1>;
+			baikal,pcie-lcru = <&pcie_lcru 1>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			ranges = <0x81000000 0x0 0x00100000 0x0 0x50000000 0x0 0x100000>,   /* I/O */
+				 <0x82000000 0x0 0x40000000 0x5 0x00000000 0x0 0x40000000>; /* 32b non-prefetchable memory */
+			msi-parent = <&its 0x0>;
+			msi-map = <0x0 &its 0x0 0x10000>;
+			num-lanes = <4>;
+			num-viewport = <4>;
+			bus-range = <0x0 0xff>;
+			status = "disabled";
+		};
+
+		pcie2: pcie@2220000 { /* PCIe x8 */
+			compatible = "baikal,pcie-m", "snps,dw-pcie";
+			reg = <0x0 0x02220000 0x0 0x1000>,   /* RC config space */
+			      <0x0 0x60000000 0x0 0x100000>; /* PCI config space */
+			reg-names = "dbi", "config";
+			interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, /* AER */
+				     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; /* MSI */
+			#interrupt-cells = <1>;
+			baikal,pcie-lcru = <&pcie_lcru 2>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			ranges = <0x81000000 0x0 0x00200000 0x0 0x60100000 0x0 0x100000>,   /* I/O */
+				 <0x82000000 0x0 0x80000000 0x6 0x00000000 0x0 0x80000000>; /* 32b non-prefetchable memory */
+			msi-parent = <&its 0x0>;
+			msi-map = <0x0 &its 0x0 0x10000>;
+			num-lanes = <8>;
+			num-viewport = <4>;
+			bus-range = <0x0 0xff>;
+			status = "disabled";
+		};
+
+		ccn: ccn@9000000 {
+			compatible = "arm,ccn-504";
+			reg = <0x0 0x9000000 0 0x1000000>;
+			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pvt0: pvt0@28200000 {
+			compatible = "baikal,pvt";
+			reg = <0x0 0x28200000 0x0 0x10000>;
+			pvt_id = <0>;
+			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		pvt1: pvt1@c200000 {
+			compatible = "baikal,pvt";
+			reg = <0x0 0xc200000 0x0 0x10000>;
+			pvt_id = <1>;
+			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		pvt2: pvt2@a200000 {
+			compatible = "baikal,pvt";
+			reg = <0x0 0xa200000 0x0 0x10000>;
+			pvt_id = <2>;
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		pvt3: pvt3@26200000 {
+			compatible = "baikal,pvt";
+			reg = <0x0 0x26200000 0x0 0x10000>;
+			pvt_id = <3>;
+			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		pvt_mali: pvt_mali@2a060000 {
+			compatible = "baikal,pvt";
+			reg = <0x0 0x2a060000 0x0 0x10000>;
+			pvt_id = <4>;
+			interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		/* AVLSP: GPIO32 (20200000, 10000, SPI_131_H) */
+		gpio: gpio@20200000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x0 0x20200000 0x0 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+
+			porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				#gpio-cells = <2>;
+				gpio-controller;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+				#interrupt-cells = <2>;
+				interrupt-controller;
+				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		/* AVLSP: SPI (20210000, 10000, SPI_132_H) */
+		spi0: spi@20210000 {
+			compatible = "snps,dw-apb-ssi", "snps,dw-spi";
+			reg = <0x0 0x20210000 0x0 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu0_avlsp 4>;
+			clock-names = "soc_spiclk";
+			status = "disabled";
+		};
+
+		/* AVLSP: I2S (20220000, 1000, SPI_136-139_H) */
+		i2s: i2s@20220000 {
+			compatible = "snps,designware-i2s";
+			reg = <0x0 0x20220000 0x0 0x10000>;
+			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* rx_da */
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, /* rx_or */
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, /* tx_emp */
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; /* tx_or */
+			/*dmas = <&dma 2>, <&dma 3>;*/
+			/*dma-names = "tx", "rx";*/
+			/*#sound-dai-cells = <0>;*/
+			clocks = <&soc_tmp_clk>;
+			clock-names = "i2sclk";
+			status = "disabled";
+		};
+
+		/* AVLSP: UART1 (20230000, 10000, SPI_133_H) */
+		uart0: serial0@20230000 {
+			compatible = "snps,dw-apb-uart"; /* "snps,uart-16550-compatible" */
+			reg = <0x0 0x20230000 0x0 0x10000>;
+			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&cmu0_avlsp 1>, <&apb_clk>;
+			clock-names = "soc_uartclk", "apb_pclk";
+			/*dcd-override;*/
+			/*dsr-override;*/
+			/*cts-override;*/
+			/*ri-override;*/
+			status = "disabled";
+		};
+
+		/* AVLSP: UART2 (20240000, 10000, SPI_134_H) */
+		uart1: serial1@20240000 {
+			compatible = "snps,dw-apb-uart"; /* "snps,uart-16550-compatible" */
+			reg = <0x0 0x20240000 0x0 0x10000>;
+			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&cmu0_avlsp 2>, <&apb_clk>;
+			clock-names = "soc_uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		/* AVLSP: I2C1 (20250000, 10000, SPI_140_H) */
+		i2c0: i2c0@20250000 {
+			compatible = "snps,designware-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x20250000 0x0 0x10000>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-sda-hold-time-ns = <500>;
+			clock-frequency = <400000>;
+			clocks = <&i2c_clk>;
+			clock-names = "soc_i2cclk";
+			status = "disabled";
+		};
+
+		/* AVLSP: I2C2 (20260000, 10000, SPI_141_H) */
+		i2c1: i2c1@20260000 {
+			compatible = "snps,designware-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x20260000 0x0 0x10000>;
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-sda-hold-time-ns = <500>;
+			clock-frequency = <400000>;
+			clocks = <&i2c_clk>;
+			clock-names = "soc_i2cclk";
+			status = "disabled";
+		};
+
+		/* AVLSP: SMBus1 (20270000, 10000, SPI_142_?) */
+		smbus0: smbus0@20270000 {
+			compatible = "be,smbus";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x20270000 0x0 0x10000>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <100000>;
+			clocks = <&smbus_clk>;
+			clock-names = "soc_smbusclk";
+			status = "disabled";
+		};
+
+		/* AVLSP: SMBus2 (20280000, 10000, SPI_143_?) */
+		smbus1: smbus1@20280000 {
+			compatible = "be,smbus";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x20280000 0x0 0x10000>;
+			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <100000>;
+			clocks = <&smbus_clk>;
+			clock-names = "soc_smbusclk";
+			status = "disabled";
+		};
+
+		/* AVLSP: Timers (20290000, 10000, SPI_127_L) */
+		timer1: timer1@20290000 {
+			compatible = "snps,dw-apb-timer-osc";
+			reg = <0x0 0x20290000 0x0 0x14>;
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <50000000>;
+			clocks = <&timer1_clk>;
+			clock-names = "soc_timer1clk";
+			status = "disabled";
+		};
+
+		/* AVLSP: Timers (20290000, 10000, SPI_128_L) */
+		timer2: timer2@20290014 {
+			compatible = "snps,dw-apb-timer-sp";
+			reg = <0x0 0x20290014 0x0 0x14>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <50000000>;
+			clocks = <&timer2_clk>;
+			clock-names = "soc_timer2clk";
+			status = "disabled";
+		};
+
+		/* AVLSP: Timers (20290000, 10000, SPI_129_L) */
+		timer3: timer3@20290028 {
+			compatible = "snps,dw-apb-timer-sp";
+			reg = <0x0 0x20290028 0x0 0x14>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <50000000>;
+			clocks = <&timer3_clk>;
+			clock-names = "soc_timer3clk";
+			status = "disabled";
+		};
+
+		/* AVLSP: Timers (20290000, 10000, SPI_130_L) */
+		timer4: timer4@2029003c {
+			compatible = "snps,dw-apb-timer-sp";
+			reg = <0x0 0x2029003c 0x0 0x14>;
+			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <50000000>;
+			clocks = <&timer4_clk>;
+			clock-names = "soc_timer4clk";
+			status = "disabled";
+		};
+
+		/* AVLSP: eSPI (202a0000, 10000, SPI_135_?) */
+		espi0: espi0@202a0000 {
+			compatible = "be,espi";
+			reg = <0x0 0x202a0000 0x0 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu0_avlsp 5>;
+			clock-names = "soc_espiclk";
+			status = "disabled";
+			/*
+			 * Block Configuration:
+			 * - master/slave
+			 * - 32-bit APB slave
+			 * - tx-fifo = rx-fifo = 256 byte
+			 * - 4 SPI IO channels
+			 * - 8 slave select IO channels
+			 * - DMA - missing
+			 * - M-flash controller - missing
+			 */
+		};
+
+		/* AVLSP: DMAC (202b0000, 10000, SPI_41-80_H) */
+		lsdma: dma@202b0000 {
+			compatible = "snps,dma-spear1340";
+			reg = <0x0 0x202b0000 0x0 0x10000>;
+			/* TODO: interrupts */
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			dma-channels = <8>;
+			dma-requests = <16>;
+			dma-masters = <2>;
+			#dma-cells = <3>;
+			chan_allocation_order = <1>;
+			chan_priority = <1>;
+			block_size = <0xfff>;
+			data_width = <3 3 0 0>;
+			clocks = <&soc_tmp_clk>;
+			clock-names = "tmpclk";
+			status = "disabled";
+		};
+
+		/* AVLSP: HDA (202c0000, 10000, SPI_86_H) */
+		hda: hda@202c0000 {
+			compatible = "be,cw-hda";
+			reg = <0x0 0x202c0000 0x0 0x1000>;
+			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu0_avlsp 15>, <&cmu0_avlsp 16>;
+			clock-names = "hda_sys_clk", "hda_clk48";
+			status = "disabled";
+		};
+
+		/* AVLSP: VDU (202d0000, 10000, SPI_144-145_?) */
+		vdu0: vdu_lvds@202d0000 {
+			compatible = "baikal,vdu";
+			reg = <0x0 0x202d0000 0x0 0x1000>;
+			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, /* VDU INTR */
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* VDU INTR_CDD */
+			clocks = <&cmu1_avlsp_div7>;
+			clock-names = "pclk";
+			lvds-out;
+			status = "disabled";
+		};
+
+		/* AVLSP: SD/eMMC (202e0000, 10000, SPI_83-84_H) */
+		mmc0: mmc@202e0000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0x0 0x202e0000 0x0 0x10000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "bus", "core";
+			clocks = <&cmu0_avlsp 18>, <&cmu0_avlsp 19>;
+			status = "disabled";
+		};
+
+		vdec: vdec@24200000 {
+			compatible = "baikal,d5500-vxd";
+			reg = <0x0 0x24200000 0x0 0x10000>;
+			interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		gpu: gpu@2a200000 {
+			compatible = "arm,mali-midgard", "arm,mali-t628";
+			#cooling-cells = <2>; /* min followed by max */
+			reg = <0x0 0x2a200000 0x0 0x4000>;
+			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "job", "mmu", "gpu";
+			clocks = <&cmu_mali>;
+			clock-names = "gpuclk";
+			operating-points-v2 = <&gpu_opp_table>;
+		};
+
+		/* USB MM: USB2 (2c400000, 100000, SPI_267-268_H, SPI_277_H) */
+		usb2: usb2@2c400000 {
+			compatible = "be,baikal-dwc3";
+			status = "disabled";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			clocks = <&usb_clk>;
+			clock-names = "usb";
+			dma-coherent;
+
+			dwc3@2c400000 {
+				compatible = "snps,dwc3", "synopsys,dwc3", "generic-xhci";
+				reg = <0x0 0x2c400000 0x0 0x100000>;
+				interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+				dr_mode = "host";
+				dma-coherent;
+				maximum-speed = "high-speed";
+			};
+		};
+
+		/* USB MM: USB3 (2c500000, 100000, SPI_269-276_H, SPI_278_H) */
+		usb3: usb3@2c500000 {
+			compatible = "be,baikal-dwc3";
+			status = "disabled";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			clocks = <&usb_clk>;
+			clock-names = "usb";
+
+			dwc3@2c500000 {
+				compatible = "snps,dwc3", "synopsys,dwc3", "generic-xhci";
+				reg = <0x0 0x2c500000 0x0 0x100000>;
+				interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+				dr_mode = "host";
+				dma-coherent;
+			};
+		};
+
+		/* USB MM: SATA0 (2c600000, 10000, SPI_265_H) */
+		sata0: sata0@2c600000 {
+			compatible = "snps,dwc-ahci", "generic-ahci";
+			reg = <0x0 0x2c600000 0 0x10000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+			ports-implemented = <1>;
+			dma-coherent;
+			clocks = <&soc_faxiclk>;
+			clock-names = "sataclk";
+			status = "disabled";
+		};
+
+		/* USB MM: SATA1 (2c610000, 10000, SPI_266_H) */
+		sata1: sata1@2c610000 {
+			compatible = "snps,dwc-ahci", "generic-ahci";
+			reg = <0x0 0x2c610000 0 0x10000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+			ports-implemented = <1>;
+			dma-coherent;
+			clocks = <&soc_faxiclk>;
+			clock-names = "sataclk";
+			status = "disabled";
+		};
+
+		/* DMA-330: DMAC ("secure",     2c620000, 10000, SPI_255-263_H) */
+		/*               ("non-secure", 2c630000, 10000, ?) */
+		dma: dma@2c620000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x0 0x2c620000 0 0x1000>;
+			#dma-cells = <1>;
+			#dma-channels = <8>;
+			#dma-requests = <32>;
+			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&soc_faxiclk>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+		};
+
+		gic: interrupt-controller@2d000000 {
+			compatible = "arm,gic-v3";
+			#interrupt-cells = <3>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			interrupt-controller;
+			reg = <0x0 0x2d000000 0x0 0x10000>,  /* GICD */
+			      <0x0 0x2d100000 0x0 0x200000>, /* GICR */
+			      <0x0 0x10200000 0x0 0x2000>,   /* GICC */
+			      <0x0 0x10210000 0x0 0x1000>,   /* GICH */
+			      <0x0 0x10220000 0x0 0x2000>;   /* GICV */
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+			its: its@2d020000 {
+				compatible = "arm,gic-v3-its";
+				msi-controller;
+				#msi-cells = <1>;
+				reg = <0x0 0x2d020000 0x0 0x20000>; /* GITS */
+			};
+		};
+
+		axi_gmac: stmmac-axi-config0 {
+			snps,wr_osr_lmt = <0x0>;
+			snps,rd_osr_lmt = <0x0>;
+			snps,blen = <0 0 0 0 0 0 4>;
+		};
+
+		gmac0: eth0@30240000 {
+			compatible = "be,dwmac", "snps,dwmac-3.710", "snps,dwmac";
+			reg = <0x0 0x30240000 0x0 0x10000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			max-speed = <1000>;
+			clocks = <&soc_ethclk>, <&cmu0_xgbe 10>;
+			clock-names = "stmmaceth", "tx2_clk";
+			mac-address = [ 00 00 00 00 00 00 ];
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			phy-mode = "rgmii-id";
+			phy-handle = <&gmac0_phy>;
+			snps,fixed-burst;
+			snps,axi-config = <&axi_gmac>;
+			snps,no-pbl-x8;
+			snps,txpbl = <4>;
+			snps,rxpbl = <4>;
+			snps,reset-delays-us = <0 10200 1000>;
+			status = "disabled";
+			dma-coherent;
+
+			gmdio0: gmac0_mdio {
+				compatible = "snps,dwmac-mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				gmac0_phy: ethernet-phy@3 {
+					compatible = "micrel,ksz9031", "ethernet-phy-id0022.1620", "ethernet-phy-ieee802.3-c22";
+					reg = <0x3>;
+					txd0-skew-ps = <0>;
+					txd1-skew-ps = <0>;
+					txd2-skew-ps = <0>;
+					txd3-skew-ps = <0>;
+					txc-skew-ps = <0xff>;
+				};
+			};
+		};
+
+		gmac1: eth1@30250000 {
+			compatible = "be,dwmac", "snps,dwmac-3.710", "snps,dwmac";
+			reg = <0x0 0x30250000 0x0 0x10000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			max-speed = <1000>;
+			clocks = <&soc_ethclk>, <&cmu0_xgbe 13>;
+			clock-names = "stmmaceth", "tx2_clk";
+			mac-address = [ 00 00 00 00 00 00 ];
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			phy-mode = "rgmii-id";
+			phy-handle = <&gmac1_phy>;
+			snps,fixed-burst;
+			snps,axi-config = <&axi_gmac>;
+			snps,no-pbl-x8;
+			snps,txpbl = <4>;
+			snps,rxpbl = <4>;
+			snps,reset-delays-us = <0 10200 1000>;
+			status = "disabled";
+			dma-coherent;
+
+			gmdio1: gmac1_mdio {
+				compatible = "snps,dwmac-mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				gmac1_phy: ethernet-phy@3 {
+					compatible = "micrel,ksz9031", "ethernet-phy-id0022.1620", "ethernet-phy-ieee802.3-c22";
+					reg = <0x3>;
+					txd0-skew-ps = <0>;
+					txd1-skew-ps = <0>;
+					txd2-skew-ps = <0>;
+					txd3-skew-ps = <0>;
+					txc-skew-ps = <0xff>;
+				};
+			};
+		};
+
+		/* Baikal internal MDIO */
+		mdio0: be-mdio {
+			compatible = "be,mdio-gpio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			mdc-pin = <&porta 30 GPIO_ACTIVE_HIGH>;
+			mdio-pin = <&porta 29 GPIO_ACTIVE_HIGH>;
+			clocks = <&gpio_clk>;
+			clock-names = "gpioclk";
+
+			mv_ch0: ethernet-phy@c {
+				compatible = "marvell,88x2222", "ethernet-phy-ieee802.3-c45";
+				reg = <0x0c>;
+				phy-mode = "xgmii";
+				mv,line-mode = "KR";
+				mv,host-mode = "KX4";
+			};
+
+			mv_ch2: ethernet-phy@e {
+				compatible = "marvell,88x2222", "ethernet-phy-ieee802.3-c45";
+				reg = <0x0e>;
+				phy-mode = "xgmii";
+				mv,line-mode = "KR";
+				mv,host-mode = "KX4";
+			};
+		};
+
+		/* XGMAC0 */
+		xgmac0: eth2@30200000 {
+			compatible = "amd,xgbe-seattle-v1a";
+			reg = <0x0 0x30200000 0x0 0x10000>,
+			      <0x0 0x30210000 0x0 0x10000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
+			fsl,num-rx-queues=<3>;
+			clocks = <&soc_xgbeclk>, <&soc_xgbeclk>, <&soc_xgbeclk>;
+			clock-names = "dma_clk", "ptp_clk", "xgbe_clk";
+			phy-mode = "xgmii";
+			mac-address = [ 00 20 13 ba 1c a1 ];
+			local-mac-address = [ 00 20 13 ba 1c a1 ];
+			be,pcs-mode = "KX4";
+			ext-phy-handle = <&mv_ch0>;
+			status = "disabled";
+			amd,per-channel-interrupt;
+			amd,speed-set = <0>;
+			#stream-id-cells = <16>;
+		};
+
+		/* XGMAC1 */
+		xgmac1: eth3@30220000 {
+			compatible = "amd,xgbe-seattle-v1a";
+			reg = <0x0 0x30220000 0x0 0x10000>,
+			      <0x0 0x30230000 0x0 0x10000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
+			fsl,num-rx-queues=<3>;
+			clocks = <&soc_xgbeclk>, <&soc_xgbeclk>, <&soc_xgbeclk>;
+			clock-names = "dma_clk", "ptp_clk", "xgbe_clk";
+			phy-mode = "xgmii";
+			mac-address = [ 00 20 13 ba 1c a2 ];
+			local-mac-address = [ 00 20 13 ba 1c a2 ];
+			be,pcs-mode = "KX4";
+			ext-phy-handle = <&mv_ch2>;
+			status = "disabled";
+			amd,per-channel-interrupt;
+			amd,speed-set = <0>;
+			#stream-id-cells = <16>;
+		 };
+
+		/* HDMI VDU (30260000, 10000, SPI_361-362_?) */
+		vdu1: vdu_hdmi@30260000 {
+			compatible = "baikal,vdu";
+			reg = <0x0 0x30260000 0x0 0x1000>;
+			interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, /* VDU INTR */
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; /* VDU INTR_CDD */
+			clocks = <&cmu1_xgbe 0>;
+			clock-names = "pclk";
+			status = "disabled";
+
+			port {
+				vdu_hdmi_out: endpoint {
+					remote-endpoint = <&hdmi_tx_in>;
+				};
+			};
+		};
+
+		hdmi: hdmi@30280000 {
+			compatible = "baikal,hdmi";
+			reg = <0 0x30280000 0 0x20000>;
+			reg-io-width = <4>;
+			interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu0_xgbe 0>, <&cmu0_xgbe 17>;
+			clock-names = "iahb", "isfr";
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				port@0 {
+					reg = <0>;
+					hdmi_tx_in: endpoint {
+						remote-endpoint = <&vdu_hdmi_out>;
+					};
+				};
+				port@1 {
+					reg = <1>;
+					hdmi_tx_out: endpoint {
+						remote-endpoint = <&hdmi_con>;
+					};
+				};
+			};
+		};
+	}; /* end of soc node */
+
+	hdmi-out {
+		compatible = "hdmi-connector";
+		label = "HDMI0 OUT";
+		type = "a";
+
+		port {
+			hdmi_con: endpoint {
+				remote-endpoint = <&hdmi_tx_out>;
+			};
+		};
+	};
+};
-- 
2.32.0