* [d-kernel] [PATCH 1/3] arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588
2026-02-09 11:50 [d-kernel] [PATCH 0/3] Additional patches for HDMI0 on RK3588, kernels 6.12 Daniil Gnusarev
@ 2026-02-09 11:50 ` Daniil Gnusarev
2026-02-09 11:50 ` [d-kernel] [PATCH 2/3] arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 " Daniil Gnusarev
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Daniil Gnusarev @ 2026-02-09 11:50 UTC (permalink / raw)
To: gnusarevda, devel-kernel
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock
provider support"), the HDMI PHY PLL can be used as an alternative and
more accurate pixel clock source for VOP2 to improve display modes
handling on RK3588 SoC.
Add the missing #clock-cells property to allow using the clock provider
functionality of HDMI0 PHY.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-4-d71c6a196e58@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit d0f17738778c12be629ba77ff00c43c3e9eb8428)
Signed-off-by: Daniil Gnusarev <gnusarevda@basealt.ru>
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 3b02d8c5bf4d3..fed1128671b0f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -2811,6 +2811,7 @@ hdptxphy_hdmi0: phy@fed60000 {
reg = <0x0 0xfed60000 0x0 0x2000>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
clock-names = "ref", "apb";
+ #clock-cells = <0>;
#phy-cells = <0>;
resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
<&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
--
2.42.2
^ permalink raw reply [flat|nested] 5+ messages in thread* [d-kernel] [PATCH 2/3] arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588
2026-02-09 11:50 [d-kernel] [PATCH 0/3] Additional patches for HDMI0 on RK3588, kernels 6.12 Daniil Gnusarev
2026-02-09 11:50 ` [d-kernel] [PATCH 1/3] arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588 Daniil Gnusarev
@ 2026-02-09 11:50 ` Daniil Gnusarev
2026-02-09 11:50 ` [d-kernel] [PATCH 3/3] arm64: dts: rockchip: Adjust the HDMI DDC IO driver strength for rk3588 Daniil Gnusarev
2026-02-09 16:21 ` [d-kernel] [PATCH 0/3] Additional patches for HDMI0 on RK3588, kernels 6.12 Vitaly Chikunov
3 siblings, 0 replies; 5+ messages in thread
From: Daniil Gnusarev @ 2026-02-09 11:50 UTC (permalink / raw)
To: gnusarevda, devel-kernel
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
more accurate pixel clock source to improve handling of display modes up
to 4K@60Hz on video ports 0, 1 and 2.
For now only HDMI0 output is supported, hence add the related PLL clock.
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-5-d71c6a196e58@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit eb4262203d7d85eb7b6f2696816db272e41f5464)
Signed-off-by: Daniil Gnusarev <gnusarevda@basealt.ru>
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index fed1128671b0f..030afd5f64448 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1260,14 +1260,16 @@ vop: vop@fdd90000 {
<&cru DCLK_VOP1>,
<&cru DCLK_VOP2>,
<&cru DCLK_VOP3>,
- <&cru PCLK_VOP_ROOT>;
+ <&cru PCLK_VOP_ROOT>,
+ <&hdptxphy_hdmi0>;
clock-names = "aclk",
"hclk",
"dclk_vp0",
"dclk_vp1",
"dclk_vp2",
"dclk_vp3",
- "pclk_vop";
+ "pclk_vop",
+ "pll_hdmiphy0";
iommus = <&vop_mmu>;
power-domains = <&power RK3588_PD_VOP>;
rockchip,grf = <&sys_grf>;
--
2.42.2
^ permalink raw reply [flat|nested] 5+ messages in thread* [d-kernel] [PATCH 3/3] arm64: dts: rockchip: Adjust the HDMI DDC IO driver strength for rk3588
2026-02-09 11:50 [d-kernel] [PATCH 0/3] Additional patches for HDMI0 on RK3588, kernels 6.12 Daniil Gnusarev
2026-02-09 11:50 ` [d-kernel] [PATCH 1/3] arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588 Daniil Gnusarev
2026-02-09 11:50 ` [d-kernel] [PATCH 2/3] arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 " Daniil Gnusarev
@ 2026-02-09 11:50 ` Daniil Gnusarev
2026-02-09 16:21 ` [d-kernel] [PATCH 0/3] Additional patches for HDMI0 on RK3588, kernels 6.12 Vitaly Chikunov
3 siblings, 0 replies; 5+ messages in thread
From: Daniil Gnusarev @ 2026-02-09 11:50 UTC (permalink / raw)
To: gnusarevda, devel-kernel
From: Andy Yan <andy.yan@rock-chips.com>
For the RK3588 HDMI controller, the falling edge of DDC SDA and SCL
almost coincide and cannot be adjusted by HDMI registrer, resulting
in poor compatibility of DDC communication.
An improvement of the compatibility of DDC can be done by increasing
the driver strength of SCL and decreasing the driver strength of SDA
to increase the slope of the falling edge.
It should be noted that the maximum driving strength of hdmim0_tx1_scl
is only 3, which is different from that of the other IOs.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250522020537.1884771-1-andyshrk@163.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit af9feb0b85f92d2972061224839c5fea5ee39f6d)
Signed-off-by: Daniil Gnusarev <gnusarevda@basealt.ru>
---
.../dts/rockchip/rk3588-base-pinctrl.dtsi | 20 +++++------
| 5 +--
.../boot/dts/rockchip/rockchip-pinconf.dtsi | 35 +++++++++++++++++++
3 files changed, 48 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
index d1368418502a5..e77907e637d44 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
@@ -578,14 +578,14 @@ hdmim0_tx0_hpd: hdmim0-tx0-hpd {
hdmim0_tx0_scl: hdmim0-tx0-scl {
rockchip,pins =
/* hdmim0_tx0_scl */
- <4 RK_PB7 5 &pcfg_pull_none>;
+ <4 RK_PB7 5 &pcfg_pull_none_drv_level_5_smt>;
};
/omit-if-no-ref/
hdmim0_tx0_sda: hdmim0-tx0-sda {
rockchip,pins =
/* hdmim0_tx0_sda */
- <4 RK_PC0 5 &pcfg_pull_none>;
+ <4 RK_PC0 5 &pcfg_pull_none_drv_level_1_smt>;
};
/omit-if-no-ref/
@@ -640,14 +640,14 @@ hdmim1_tx0_hpd: hdmim1-tx0-hpd {
hdmim1_tx0_scl: hdmim1-tx0-scl {
rockchip,pins =
/* hdmim1_tx0_scl */
- <0 RK_PD5 11 &pcfg_pull_none>;
+ <0 RK_PD5 11 &pcfg_pull_none_drv_level_5_smt>;
};
/omit-if-no-ref/
hdmim1_tx0_sda: hdmim1-tx0-sda {
rockchip,pins =
/* hdmim1_tx0_sda */
- <0 RK_PD4 11 &pcfg_pull_none>;
+ <0 RK_PD4 11 &pcfg_pull_none_drv_level_1_smt>;
};
/omit-if-no-ref/
@@ -668,14 +668,14 @@ hdmim1_tx1_hpd: hdmim1-tx1-hpd {
hdmim1_tx1_scl: hdmim1-tx1-scl {
rockchip,pins =
/* hdmim1_tx1_scl */
- <3 RK_PC6 5 &pcfg_pull_none>;
+ <3 RK_PC6 5 &pcfg_pull_none_drv_level_5_smt>;
};
/omit-if-no-ref/
hdmim1_tx1_sda: hdmim1-tx1-sda {
rockchip,pins =
/* hdmim1_tx1_sda */
- <3 RK_PC5 5 &pcfg_pull_none>;
+ <3 RK_PC5 5 &pcfg_pull_none_drv_level_1_smt>;
};
/omit-if-no-ref/
hdmim2_rx_cec: hdmim2-rx-cec {
@@ -709,14 +709,14 @@ hdmim2_rx_sda: hdmim2-rx-sda {
hdmim2_tx0_scl: hdmim2-tx0-scl {
rockchip,pins =
/* hdmim2_tx0_scl */
- <3 RK_PC7 5 &pcfg_pull_none>;
+ <3 RK_PC7 5 &pcfg_pull_none_drv_level_5_smt>;
};
/omit-if-no-ref/
hdmim2_tx0_sda: hdmim2-tx0-sda {
rockchip,pins =
/* hdmim2_tx0_sda */
- <3 RK_PD0 5 &pcfg_pull_none>;
+ <3 RK_PD0 5 &pcfg_pull_none_drv_level_1_smt>;
};
/omit-if-no-ref/
@@ -730,14 +730,14 @@ hdmim2_tx1_cec: hdmim2-tx1-cec {
hdmim2_tx1_scl: hdmim2-tx1-scl {
rockchip,pins =
/* hdmim2_tx1_scl */
- <1 RK_PA4 5 &pcfg_pull_none>;
+ <1 RK_PA4 5 &pcfg_pull_none_drv_level_5_smt>;
};
/omit-if-no-ref/
hdmim2_tx1_sda: hdmim2-tx1-sda {
rockchip,pins =
/* hdmim2_tx1_sda */
- <1 RK_PA3 5 &pcfg_pull_none>;
+ <1 RK_PA3 5 &pcfg_pull_none_drv_level_1_smt>;
};
/omit-if-no-ref/
--git a/arch/arm64/boot/dts/rockchip/rk3588-extra-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra-pinctrl.dtsi
index 244c66faa1614..fb48ddc04bcbd 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra-pinctrl.dtsi
@@ -160,14 +160,15 @@ hdmim0_tx1_cec: hdmim0-tx1-cec {
hdmim0_tx1_scl: hdmim0-tx1-scl {
rockchip,pins =
/* hdmim0_tx1_scl */
- <2 RK_PB5 4 &pcfg_pull_none>;
+ <2 RK_PB5 4 &pcfg_pull_none_drv_level_3_smt>;
};
/omit-if-no-ref/
hdmim0_tx1_sda: hdmim0-tx1-sda {
rockchip,pins =
/* hdmim0_tx1_sda */
- <2 RK_PB4 4 &pcfg_pull_none>;
+ <2 RK_PB4 4 &pcfg_pull_none_drv_level_1_smt>;
+
};
};
diff --git a/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi b/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi
index 5c645437b5072..b0475b7c655ae 100644
--- a/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi
@@ -332,6 +332,41 @@ pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt {
input-schmitt-enable;
};
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_1_smt: pcfg-pull-none-drv-level-1-smt {
+ bias-disable;
+ drive-strength = <1>;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_2_smt: pcfg-pull-none-drv-level-2-smt {
+ bias-disable;
+ drive-strength = <2>;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_3_smt: pcfg-pull-none-drv-level-3-smt {
+ bias-disable;
+ drive-strength = <3>;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_4_smt: pcfg-pull-none-drv-level-4-smt {
+ bias-disable;
+ drive-strength = <4>;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_5_smt: pcfg-pull-none-drv-level-5-smt {
+ bias-disable;
+ drive-strength = <5>;
+ input-schmitt-enable;
+ };
+
/omit-if-no-ref/
pcfg_output_high: pcfg-output-high {
output-high;
--
2.42.2
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [d-kernel] [PATCH 0/3] Additional patches for HDMI0 on RK3588, kernels 6.12
2026-02-09 11:50 [d-kernel] [PATCH 0/3] Additional patches for HDMI0 on RK3588, kernels 6.12 Daniil Gnusarev
` (2 preceding siblings ...)
2026-02-09 11:50 ` [d-kernel] [PATCH 3/3] arm64: dts: rockchip: Adjust the HDMI DDC IO driver strength for rk3588 Daniil Gnusarev
@ 2026-02-09 16:21 ` Vitaly Chikunov
3 siblings, 0 replies; 5+ messages in thread
From: Vitaly Chikunov @ 2026-02-09 16:21 UTC (permalink / raw)
To: ALT Linux kernel packages development
On Mon, Feb 09, 2026 at 03:50:06PM +0400, Daniil Gnusarev wrote:
> Для работы с 4K мониторами необходимы данные патчи из более новых
> версий ядра. Проводится более точная настройка частот.
> Кроме этого изменены настройки выводов DDC для более устойчивой связи.
>
> Проверял на платах rock-5b-rk3588, orange-pi-5-plus, thin_88rk-1a
>
> Andy Yan (1):
> arm64: dts: rockchip: Adjust the HDMI DDC IO driver strength for
> rk3588
>
> Cristian Ciocaltea (2):
> arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588
> arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588
Applied to 6.12/sisyphus, thanks
>
> .../dts/rockchip/rk3588-base-pinctrl.dtsi | 20 +++++------
> arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 7 ++--
> .../dts/rockchip/rk3588-extra-pinctrl.dtsi | 5 +--
> .../boot/dts/rockchip/rockchip-pinconf.dtsi | 35 +++++++++++++++++++
> 4 files changed, 53 insertions(+), 14 deletions(-)
>
> --
> 2.42.2
>
> _______________________________________________
> devel-kernel mailing list
> devel-kernel@lists.altlinux.org
> https://lists.altlinux.org/mailman/listinfo/devel-kernel
^ permalink raw reply [flat|nested] 5+ messages in thread