From: Anton Midyukov <antohami@altlinux.org>
To: devel-kernel@lists.altlinux.org
Subject: Re: [d-kernel] [PATCH] arm64: dts: add devicetree for repka pi4 optimal
Date: Thu, 8 May 2025 04:10:39 +0300
Message-ID: <804fca3b-d980-410f-9610-68d7275228ed@altlinux.org> (raw)
In-Reply-To: <o5ekecd3sdzpofbpltzjix6k5s5rsmooe57v7wtdygtcqzv2rg@6rhirplnh2gz>
08.05.2025 03:54, Vitaly Chikunov пишет:
> On Wed, May 07, 2025 at 11:50:53PM +0300, Kurachenko Anton wrote:
>> 1. Я проверял сборку и работоспособность полученного результата на ядре
>> 6.12.25-alt1.
>
> Это хорошо, спасибо.
>
>> 2. Дело в том, что загрузчик u-boot для Repka Pi 4 требует обязательного
>> наличия dtb для запуска. Сейчас нам приходится заниматься скачиванием и
>> распаковкой ядра repka4, затем извлекать нужный dtb и переносить его в
>> /boot/devicetree/$kernelversion/allwinner ядра 6.12, чтобы хотя бы
>> просто начать процесс установки. Патч призван решить эту проблему.
>
> То есть наше 6.12 начнет загружаться на repka pi4 или это для чего-то
> другого нужно?
>
Да. Будет загружаться и работать. Этого будет достаточно, чтобы установить ядро repka pi4.
Это необходимо для того, чтобы не выпускать дополнительные образы с ядром для repka pi4.
>>
>> 07.05.2025 22:39, Vitaly Chikunov пишет:
>>> Anton,
>>>
>>> On Tue, May 06, 2025 at 03:28:28PM +0300, kurachenko-urup@ya.ru wrote:
>>>> From: Anton Kurachenko <srebrov@altlinux.org>
>>>>
>>>> Patch for 6.12 kernel to resolving boot problem on repka pi4 optimal SBC with
>>>> u-boot-2020.x (u-boot-repka4). This version of u-boot requires the presence of
>>>> a dtb file.
>>>>
>>>> Patch designed specifically for ALT and never used anywhere.
>>>
>>> 1. Это изменение протестировано?
>>> 2. Зачем нужен этот патч, если есть флейворы repka/repka4?
>>>
>>> Thanks,
>>>
>>>>
>>>> The final DTS in this patch is based on the sun50i-h6-repka-pi4-optimal.dts
>>>> file, as well as modified sun50i-h6.dtsi and sun50i-h6-cpu-opp.dtsi files taken
>>>> from the official RBS repository. Also included original sun50i-h6-gpu-opp.dtsi.
>>>> Represents the result of merging these files with applying some modifications.
>>>>
>>>> Files that were used during the creation process:
>>>>
>>>> sun50i-h6-repka-pi4-optimal.dts
>>>> Link: https://gitflic.ru/project/npo_rbs/repka-os_kernel/blob?file=arch%2Farm64%2Fboot%2Fdts%2Fallwinner%2Fsun50i-h6-repka-pi4-optimal.dts
>>>>
>>>> sun50i-h6.dtsi
>>>> Link: https://gitflic.ru/project/npo_rbs/repka-os_kernel/blob?file=arch%2Farm64%2Fboot%2Fdts%2Fallwinner%2Fsun50i-h6.dtsi
>>>>
>>>> sun50i-h6-cpu-opp.dtsi
>>>> Link: https://gitflic.ru/project/npo_rbs/repka-os_kernel/blob?file=arch%2Farm64%2Fboot%2Fdts%2Fallwinner%2Fsun50i-h6-cpu-opp.dtsi
>>>>
>>>> Signed-off-by: Anton Kurachenko <srebrov@altlinux.org>
>>>> ---
>>>> arch/arm64/boot/dts/allwinner/Makefile | 1 +
>>>> .../allwinner/sun50i-h6-repka-pi4-optimal.dts | 1918 +++++++++++++++++
>>>> 2 files changed, 1919 insertions(+)
>>>> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-repka-pi4-optimal.dts
>>>>
>>>> diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
>>>> index 00bed412ee31..2df5189e0d44 100644
>>>> --- a/arch/arm64/boot/dts/allwinner/Makefile
>>>> +++ b/arch/arm64/boot/dts/allwinner/Makefile
>>>> @@ -52,3 +52,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-2024.dtb
>>>> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-h.dtb
>>>> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-plus.dtb
>>>> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-sp.dtb
>>>> +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-repka-pi4-optimal.dtb
>>>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-repka-pi4-optimal.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-repka-pi4-optimal.dts
>>>> new file mode 100644
>>>> index 000000000000..9d95297a30b8
>>>> --- /dev/null
>>>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-repka-pi4-optimal.dts
>>>> @@ -0,0 +1,1918 @@
>>>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>>>> +// based on the dts, which is:
>>>> +// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
>>>> +// Copyright (C) 2019 Ondřej Jirman <megous@megous.com>
>>>> +// Copyright (C) 2020 Igor Pecovnik <igor@armbian.com>
>>>> +// Copyright (C) 2020 Clément Péron <peron.clem@gmail.com>
>>>> +
>>>> +/dts-v1/;
>>>> +
>>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>>> +#include <dt-bindings/clock/sun50i-h6-ccu.h>
>>>> +#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
>>>> +#include <dt-bindings/clock/sun6i-rtc.h>
>>>> +#include <dt-bindings/clock/sun8i-de2.h>
>>>> +#include <dt-bindings/clock/sun8i-tcon-top.h>
>>>> +#include <dt-bindings/reset/sun50i-h6-ccu.h>
>>>> +#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
>>>> +#include <dt-bindings/reset/sun8i-de2.h>
>>>> +#include <dt-bindings/thermal/thermal.h>
>>>> +#include <dt-bindings/gpio/gpio.h>
>>>> +
>>>> +/ {
>>>> + interrupt-parent = <&gic>;
>>>> + #address-cells = <1>;
>>>> + #size-cells = <1>;
>>>> + model = "Repka-Pi4-Optimal";
>>>> + repka-freq = "1.968 GHz";
>>>> + repka-pinout = "repka-pi4-base";
>>>> + compatible = "rbs,repka-pi4", "allwinner,sun50i-h6";
>>>> +
>>>> + aliases {
>>>> + mmc0 = &mmc0;
>>>> + mmc1 = &mmc1;
>>>> + mmc2 = &mmc2;
>>>> + ethernet0 = &emac;
>>>> + serial0 = &uart0;
>>>> + serial1 = &uart1;
>>>> + serial2 = &r_uart;
>>>> +
>>>> + spi0 = &spi1;
>>>> + i2c1 = &i2c0;
>>>> + i2c2 = &i2c2;
>>>> + i2c3 = &i2c1;
>>>> + i2c4 = &i2c3;
>>>> +
>>>> + };
>>>> +
>>>> + reserved-memory {
>>>> + #address-cells = <1>;
>>>> + #size-cells = <1>;
>>>> + ranges;
>>>> +
>>>> + custom_region: region@40010000 {
>>>> + reg = <0x40010000 0x00070000>;
>>>> + no-map;
>>>> + };
>>>> + };
>>>> +
>>>> + analog: analog-codec {
>>>> + compatible = "simple-audio-card";
>>>> + simple-audio-card,format = "i2s";
>>>> + simple-audio-card,name = "ac200-audio";
>>>> + simple-audio-card,mclk-fs = <512>;
>>>> + status = "okay";
>>>> +
>>>> + simple-audio-card,cpu {
>>>> + sound-dai = <&i2s3>;
>>>> + };
>>>> +
>>>> + simple-audio-card,codec {
>>>> + sound-dai = <&ac200_codec>;
>>>> + };
>>>> + };
>>>> +
>>>> + ac200_pwm_clk: ac200_clk {
>>>> + compatible = "pwm-clock";
>>>> + #clock-cells = <0>;
>>>> + clock-frequency = <24000000>;
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&pwm1_pin>;
>>>> + pwms = <&pwm 1 42 0>;
>>>> + status = "okay";
>>>> + };
>>>> +
>>>> + cpus {
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + cpu0: cpu@0 {
>>>> + compatible = "arm,cortex-a53";
>>>> + device_type = "cpu";
>>>> + reg = <0>;
>>>> + enable-method = "psci";
>>>> + clocks = <&ccu CLK_CPUX>;
>>>> + clock-latency-ns = <244144>; /* 8 32k periods */
>>>> + #cooling-cells = <2>;
>>>> + operating-points-v2 = <&cpu_opp_table>;
>>>> + cpu-supply = <®_dcdca>;
>>>> + };
>>>> +
>>>> + cpu1: cpu@1 {
>>>> + compatible = "arm,cortex-a53";
>>>> + device_type = "cpu";
>>>> + reg = <1>;
>>>> + enable-method = "psci";
>>>> + clocks = <&ccu CLK_CPUX>;
>>>> + clock-latency-ns = <244144>; /* 8 32k periods */
>>>> + #cooling-cells = <2>;
>>>> + operating-points-v2 = <&cpu_opp_table>;
>>>> + };
>>>> +
>>>> + cpu2: cpu@2 {
>>>> + compatible = "arm,cortex-a53";
>>>> + device_type = "cpu";
>>>> + reg = <2>;
>>>> + enable-method = "psci";
>>>> + clocks = <&ccu CLK_CPUX>;
>>>> + clock-latency-ns = <244144>; /* 8 32k periods */
>>>> + #cooling-cells = <2>;
>>>> + operating-points-v2 = <&cpu_opp_table>;
>>>> + };
>>>> +
>>>> + cpu3: cpu@3 {
>>>> + compatible = "arm,cortex-a53";
>>>> + device_type = "cpu";
>>>> + reg = <3>;
>>>> + enable-method = "psci";
>>>> + clocks = <&ccu CLK_CPUX>;
>>>> + clock-latency-ns = <244144>; /* 8 32k periods */
>>>> + #cooling-cells = <2>;
>>>> + operating-points-v2 = <&cpu_opp_table>;
>>>> + };
>>>> + };
>>>> +
>>>> + de: display-engine {
>>>> + compatible = "allwinner,sun50i-h6-display-engine";
>>>> + allwinner,pipelines = <&mixer0>;
>>>> + status = "okay";
>>>> + };
>>>> +
>>>> + osc24M: osc24M_clk {
>>>> + #clock-cells = <0>;
>>>> + compatible = "fixed-clock";
>>>> + clock-frequency = <24000000>;
>>>> + clock-output-names = "osc24M";
>>>> + };
>>>> +
>>>> + pmu {
>>>> + compatible = "arm,cortex-a53-pmu";
>>>> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
>>>> + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
>>>> + };
>>>> +
>>>> + psci {
>>>> + compatible = "arm,psci-0.2";
>>>> + method = "smc";
>>>> + };
>>>> +
>>>> + scpi_protocol: scpi {
>>>> + compatible = "arm,scpi";
>>>> + mboxes = <&msgbox 2>, <&msgbox 3>;
>>>> + mbox-names = "tx", "rx";
>>>> + shmem = <&scpi_sram>;
>>>> + };
>>>> +
>>>> + sound_hdmi: sound_hdmi {
>>>> + compatible = "allwinner,sun9i-a80-hdmi-audio",
>>>> + "allwinner,sun50i-h6-hdmi-audio";
>>>> + status = "okay";
>>>> + codec {
>>>> + sound-dai = <&hdmi>;
>>>> + };
>>>> +
>>>> + cpu {
>>>> + sound-dai = <&i2s1>;
>>>> + };
>>>> + };
>>>> +
>>>> + timer {
>>>> + compatible = "arm,armv8-timer";
>>>> + arm,no-tick-in-suspend;
>>>> + interrupts = <GIC_PPI 13
>>>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>>>> + <GIC_PPI 14
>>>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>>>> + <GIC_PPI 11
>>>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
>>>> + <GIC_PPI 10
>>>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>>>> + };
>>>> +
>>>> +
>>>> + soc {
>>>> + compatible = "simple-bus";
>>>> + #address-cells = <1>;
>>>> + #size-cells = <1>;
>>>> + ranges;
>>>> +
>>>> + bus@1000000 {
>>>> + compatible = "allwinner,sun50i-h6-de3",
>>>> + "allwinner,sun50i-a64-de2";
>>>> + reg = <0x1000000 0x400000>;
>>>> + allwinner,sram = <&de2_sram 1>;
>>>> + #address-cells = <1>;
>>>> + #size-cells = <1>;
>>>> + ranges = <0 0x1000000 0x400000>;
>>>> +
>>>> + display_clocks: clock@0 {
>>>> + compatible = "allwinner,sun50i-h6-de3-clk";
>>>> + reg = <0x0 0x10000>;
>>>> + clocks = <&ccu CLK_BUS_DE>,
>>>> + <&ccu CLK_DE>;
>>>> + clock-names = "bus",
>>>> + "mod";
>>>> + resets = <&ccu RST_BUS_DE>;
>>>> + #clock-cells = <1>;
>>>> + #reset-cells = <1>;
>>>> + };
>>>> +
>>>> + mixer0: mixer@100000 {
>>>> + compatible = "allwinner,sun50i-h6-de3-mixer-0";
>>>> + reg = <0x100000 0x100000>;
>>>> + clocks = <&display_clocks CLK_BUS_MIXER0>,
>>>> + <&display_clocks CLK_MIXER0>;
>>>> + clock-names = "bus",
>>>> + "mod";
>>>> + resets = <&display_clocks RST_MIXER0>;
>>>> + iommus = <&iommu 0>;
>>>> +
>>>> + ports {
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + mixer0_out: port@1 {
>>>> + reg = <1>;
>>>> +
>>>> + mixer0_out_tcon_top_mixer0: endpoint {
>>>> + remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> +
>>>> + video-codec-g2@1c00000 {
>>>> + compatible = "allwinner,sun50i-h6-vpu-g2";
>>>> + reg = <0x01c00000 0x1000>;
>>>> + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>;
>>>> + clock-names = "bus", "mod";
>>>> + resets = <&ccu RST_BUS_VP9>;
>>>> + iommus = <&iommu 5>;
>>>> + };
>>>> +
>>>> + deinterlace: deinterlace@1420000 {
>>>> + compatible = "allwinner,sun50i-h6-deinterlace";
>>>> + reg = <0x01420000 0x2000>;
>>>> + clocks = <&ccu CLK_BUS_DEINTERLACE>,
>>>> + <&ccu CLK_DEINTERLACE>,
>>>> + <&ccu CLK_MBUS_DEINTERLACE>;
>>>> + clock-names = "bus", "mod", "ram";
>>>> + resets = <&ccu RST_BUS_DEINTERLACE>;
>>>> + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
>>>> + iommus = <&iommu 2>;
>>>> + };
>>>> +
>>>> + video-codec@1c0e000 {
>>>> + compatible = "allwinner,sun50i-h6-video-engine";
>>>> + reg = <0x01c0e000 0x2000>;
>>>> + clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
>>>> + <&ccu CLK_MBUS_VE>;
>>>> + clock-names = "ahb", "mod", "ram";
>>>> + resets = <&ccu RST_BUS_VE>;
>>>> + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
>>>> + allwinner,sram = <&ve_sram 1>;
>>>> + iommus = <&iommu 1>, <&iommu 3>;
>>>> + };
>>>> +
>>>> + gpu: gpu@1800000 {
>>>> + compatible = "allwinner,sun50i-h6-mali",
>>>> + "arm,mali-t720";
>>>> + reg = <0x01800000 0x4000>;
>>>> + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
>>>> + interrupt-names = "job", "mmu", "gpu";
>>>> + clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
>>>> + clock-names = "core", "bus";
>>>> + resets = <&ccu RST_BUS_GPU>;
>>>> + #cooling-cells = <2>;
>>>> + status = "okay";
>>>> + operating-points-v2 = <&gpu_opp_table>;
>>>> + mali-supply = <®_dcdcc>;
>>>> + };
>>>> +
>>>> + crypto: crypto@1904000 {
>>>> + compatible = "allwinner,sun50i-h6-crypto";
>>>> + reg = <0x01904000 0x1000>;
>>>> + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>;
>>>> + clock-names = "bus", "mod", "ram";
>>>> + resets = <&ccu RST_BUS_CE>;
>>>> + };
>>>> +
>>>> + syscon: syscon@3000000 {
>>>> + compatible = "allwinner,sun50i-h6-system-control",
>>>> + "allwinner,sun50i-a64-system-control";
>>>> + reg = <0x03000000 0x1000>;
>>>> + #address-cells = <1>;
>>>> + #size-cells = <1>;
>>>> + ranges;
>>>> +
>>>> + sram_a2: sram@100000 {
>>>> + compatible = "mmio-sram";
>>>> + reg = <0x00100000 0x18000>;
>>>> + #address-cells = <1>;
>>>> + #size-cells = <1>;
>>>> + ranges = <0 0x00100000 0x18000>;
>>>> +
>>>> + scpi_sram: scp-shmem@17c00 {
>>>> + compatible = "arm,scp-shmem";
>>>> + reg = <0x17c00 0x200>;
>>>> + };
>>>> + };
>>>> +
>>>> + sram_c: sram@28000 {
>>>> + compatible = "mmio-sram";
>>>> + reg = <0x00028000 0x1e000>;
>>>> + #address-cells = <1>;
>>>> + #size-cells = <1>;
>>>> + ranges = <0 0x00028000 0x1e000>;
>>>> +
>>>> + de2_sram: sram-section@0 {
>>>> + compatible = "allwinner,sun50i-h6-sram-c",
>>>> + "allwinner,sun50i-a64-sram-c";
>>>> + reg = <0x0000 0x1e000>;
>>>> + };
>>>> + };
>>>> +
>>>> + sram_c1: sram@1a00000 {
>>>> + compatible = "mmio-sram";
>>>> + reg = <0x01a00000 0x200000>;
>>>> + #address-cells = <1>;
>>>> + #size-cells = <1>;
>>>> + ranges = <0 0x01a00000 0x200000>;
>>>> +
>>>> + ve_sram: sram-section@0 {
>>>> + compatible = "allwinner,sun50i-h6-sram-c1",
>>>> + "allwinner,sun4i-a10-sram-c1";
>>>> + reg = <0x000000 0x200000>;
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + ccu: clock@3001000 {
>>>> + compatible = "allwinner,sun50i-h6-ccu";
>>>> + reg = <0x03001000 0x1000>;
>>>> + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>;
>>>> + clock-names = "hosc", "losc", "iosc";
>>>> + protected-clocks = <CLK_BUS_MSGBOX>;
>>>> + #clock-cells = <1>;
>>>> + #reset-cells = <1>;
>>>> + };
>>>> +
>>>> + dma: dma-controller@3002000 {
>>>> + compatible = "allwinner,sun50i-h6-dma";
>>>> + reg = <0x03002000 0x1000>;
>>>> + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
>>>> + clock-names = "bus", "mbus";
>>>> + dma-channels = <16>;
>>>> + dma-requests = <46>;
>>>> + resets = <&ccu RST_BUS_DMA>;
>>>> + #dma-cells = <1>;
>>>> + };
>>>> +
>>>> + msgbox: mailbox@3003000 {
>>>> + compatible = "allwinner,sun50i-h6-msgbox",
>>>> + "allwinner,sun6i-a31-msgbox";
>>>> + reg = <0x03003000 0x1000>;
>>>> + clocks = <&ccu CLK_BUS_MSGBOX>;
>>>> + resets = <&ccu RST_BUS_MSGBOX>;
>>>> + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
>>>> + #mbox-cells = <1>;
>>>> + };
>>>> +
>>>> + gic: interrupt-controller@3021000 {
>>>> + compatible = "arm,gic-400";
>>>> + reg = <0x03021000 0x1000>,
>>>> + <0x03022000 0x2000>,
>>>> + <0x03024000 0x2000>,
>>>> + <0x03026000 0x2000>;
>>>> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>>>> + interrupt-controller;
>>>> + #interrupt-cells = <3>;
>>>> + };
>>>> +
>>>> + sid: efuse@3006000 {
>>>> + compatible = "allwinner,sun50i-h6-sid";
>>>> + reg = <0x03006000 0x400>;
>>>> + #address-cells = <1>;
>>>> + #size-cells = <1>;
>>>> +
>>>> + ths_calibration: thermal-sensor-calibration@14 {
>>>> + reg = <0x14 0x8>;
>>>> + };
>>>> +
>>>> + cpu_speed_grade: cpu-speed-grade@1c {
>>>> + reg = <0x1c 0x4>;
>>>> + };
>>>> +
>>>> + ephy_calib: ephy_calib@2c {
>>>> + reg = <0x2c 0x2>;
>>>> + };
>>>> +
>>>> + ac200_bg: ac200_bg@30 {
>>>> + reg = <0x30 0x2>;
>>>> + };
>>>> + };
>>>> +
>>>> + timer@3009000 {
>>>> + compatible = "allwinner,sun50i-h6-timer",
>>>> + "allwinner,sun8i-a23-timer";
>>>> + reg = <0x03009000 0xa0>;
>>>> + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&osc24M>;
>>>> + };
>>>> +
>>>> + watchdog: watchdog@30090a0 {
>>>> + compatible = "allwinner,sun50i-h6-wdt",
>>>> + "allwinner,sun6i-a31-wdt";
>>>> + reg = <0x030090a0 0x20>;
>>>> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&osc24M>;
>>>> + /* Broken on some H6 boards */
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + pwm: pwm@300a000 {
>>>> + compatible = "allwinner,sun50i-h6-pwm";
>>>> + reg = <0x0300a000 0x400>;
>>>> + clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
>>>> + clock-names = "mod", "bus";
>>>> + resets = <&ccu RST_BUS_PWM>;
>>>> + #pwm-cells = <3>;
>>>> + status = "okay";
>>>> + };
>>>> +
>>>> + pio: pinctrl@300b000 {
>>>> + compatible = "allwinner,sun50i-h6-pinctrl";
>>>> + reg = <0x0300b000 0x400>;
>>>> + interrupt-parent = <&r_intc>;
>>>> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>;
>>>> + clock-names = "apb", "hosc", "losc";
>>>> + gpio-controller;
>>>> + #gpio-cells = <3>;
>>>> + interrupt-controller;
>>>> + #interrupt-cells = <3>;
>>>> + vcc-pc-supply = <®_bldo2>;
>>>> + vcc-pd-supply = <®_cldo1>;
>>>> + vcc-pg-supply = <®_vcc_wifi_io>;
>>>> +
>>>> + /omit-if-no-ref/
>>>> + ext_rgmii_pins: rgmii-pins {
>>>> + pins = "PD0", "PD1", "PD2", "PD3", "PD4",
>>>> + "PD5", "PD7", "PD8", "PD9", "PD10",
>>>> + "PD11", "PD12", "PD13", "PD19", "PD20";
>>>> + function = "emac";
>>>> + drive-strength = <40>;
>>>> + };
>>>> +
>>>> + ext_rmii_pins: rmii_pins {
>>>> + pins = "PA0", "PA1", "PA2", "PA3", "PA4",
>>>> + "PA5", "PA6", "PA7", "PA8", "PA9";
>>>> + function = "emac";
>>>> + drive-strength = <40>;
>>>> + };
>>>> +
>>>> + hdmi_pins: hdmi-pins {
>>>> + pins = "PH8", "PH9", "PH10";
>>>> + function = "hdmi";
>>>> + };
>>>> +
>>>> + i2c0_pins: i2c0-pins {
>>>> + pins = "PD25", "PD26";
>>>> + function = "i2c0";
>>>> + };
>>>> +
>>>> + i2c1_pins: i2c1-pins {
>>>> + pins = "PH5", "PH6";
>>>> + function = "i2c1";
>>>> + };
>>>> +
>>>> + i2c2_pins: i2c2-pins {
>>>> + pins = "PD23", "PD24";
>>>> + function = "i2c2";
>>>> + };
>>>> +
>>>> + i2c3_pins: i2c3-pins {
>>>> + pins = "PB17", "PB18";
>>>> + function = "i2c3";
>>>> + bias-pull-up;
>>>> + };
>>>> +
>>>> + i2s3_pins: i2s3-pins {
>>>> + pins = "PB12", "PB13", "PB14", "PB15", "PB16";
>>>> + function = "i2s3";
>>>> + };
>>>> +
>>>> + mmc0_pins: mmc0-pins {
>>>> + pins = "PF0", "PF1", "PF2", "PF3",
>>>> + "PF4", "PF5";
>>>> + function = "mmc0";
>>>> + drive-strength = <30>;
>>>> + bias-pull-up;
>>>> + };
>>>> +
>>>> + /omit-if-no-ref/
>>>> + mmc1_pins: mmc1-pins {
>>>> + pins = "PG0", "PG1", "PG2", "PG3",
>>>> + "PG4", "PG5";
>>>> + function = "mmc1";
>>>> + drive-strength = <30>;
>>>> + bias-pull-up;
>>>> + };
>>>> +
>>>> + /omit-if-no-ref/
>>>> + mmc2_pins: mmc2-pins {
>>>> + pins = "PC1", "PC4", "PC5", "PC6",
>>>> + "PC7", "PC8", "PC9", "PC10",
>>>> + "PC11", "PC12", "PC13", "PC14";
>>>> + function = "mmc2";
>>>> + drive-strength = <30>;
>>>> + bias-pull-up;
>>>> + };
>>>> +
>>>> + pwm1_pin: pwm1-pin {
>>>> + pins = "PB19";
>>>> + function = "pwm1";
>>>> + };
>>>> +
>>>> + pwm_pin: pwm-pin {
>>>> + pins = "PD22";
>>>> + function = "pwm";
>>>> + };
>>>> +
>>>> + /omit-if-no-ref/
>>>> + spi0_pins: spi0-pins {
>>>> + pins = "PC0", "PC2", "PC3";
>>>> + function = "spi0";
>>>> + };
>>>> +
>>>> + /* pin shared with MMC2-CMD (eMMC) */
>>>> + /omit-if-no-ref/
>>>> + spi0_cs_pin: spi0-cs-pin {
>>>> + pins = "PC5";
>>>> + function = "spi0";
>>>> + };
>>>> +
>>>> + /omit-if-no-ref/
>>>> + spi1_pins: spi1-pins {
>>>> + pins = "PH4", "PH5", "PH6";
>>>> + function = "spi1";
>>>> + };
>>>> +
>>>> + /omit-if-no-ref/
>>>> + spi1_cs_pin: spi1-cs-pin {
>>>> + pins = "PH3";
>>>> + function = "spi1";
>>>> + };
>>>> +
>>>> + /omit-if-no-ref/
>>>> + spdif_tx_pin: spdif-tx-pin {
>>>> + pins = "PH7";
>>>> + function = "spdif";
>>>> + };
>>>> +
>>>> + uart0_ph_pins: uart0-ph-pins {
>>>> + pins = "PH0", "PH1";
>>>> + function = "uart0";
>>>> + };
>>>> +
>>>> + uart1_pins: uart1-pins {
>>>> + pins = "PG6", "PG7";
>>>> + function = "uart1";
>>>> + };
>>>> +
>>>> + uart1_rts_cts_pins: uart1-rts-cts-pins {
>>>> + pins = "PG8", "PG9";
>>>> + function = "uart1";
>>>> + };
>>>> +
>>>> + uart2_pins: uart2-pins {
>>>> + pins = "PD19", "PD20";
>>>> + function = "uart2";
>>>> + };
>>>> +
>>>> + uart2_rts_cts_pins: uart2-rts-cts-pins {
>>>> + pins = "PD21", "PD22";
>>>> + function = "uart2";
>>>> + };
>>>> +
>>>> + uart3_pins: uart3-pins {
>>>> + pins = "PD23", "PD24";
>>>> + function = "uart3";
>>>> + };
>>>> +
>>>> + uart3_rts_cts_pins: uart3-rts-cts-pins {
>>>> + pins = "PD25", "PD26";
>>>> + function = "uart3";
>>>> + };
>>>> +
>>>> + i2s2_pins: i2s2-pins {
>>>> + pins = "PG10", "PG11", "PG12", "PG13";
>>>> + function = "i2s2";
>>>> + };
>>>> + };
>>>> +
>>>> + iommu: iommu@30f0000 {
>>>> + compatible = "allwinner,sun50i-h6-iommu";
>>>> + reg = <0x030f0000 0x10000>;
>>>> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&ccu CLK_BUS_IOMMU>;
>>>> + resets = <&ccu RST_BUS_IOMMU>;
>>>> + #iommu-cells = <1>;
>>>> + };
>>>> +
>>>> + mmc0: mmc@4020000 {
>>>> + compatible = "allwinner,sun50i-h6-mmc",
>>>> + "allwinner,sun50i-a64-mmc";
>>>> + reg = <0x04020000 0x1000>;
>>>> + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
>>>> + clock-names = "ahb", "mmc";
>>>> + resets = <&ccu RST_BUS_MMC0>;
>>>> + reset-names = "ahb";
>>>> + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&mmc0_pins>;
>>>> + max-frequency = <150000000>;
>>>> + status = "okay";
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> + vmmc-supply = <®_cldo1>;
>>>> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
>>>> + bus-width = <4>;
>>>> + };
>>>> +
>>>> + mmc1: mmc@4021000 {
>>>> + compatible = "allwinner,sun50i-h6-mmc",
>>>> + "allwinner,sun50i-a64-mmc";
>>>> + reg = <0x04021000 0x1000>;
>>>> + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
>>>> + clock-names = "ahb", "mmc";
>>>> + resets = <&ccu RST_BUS_MMC1>;
>>>> + reset-names = "ahb";
>>>> + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&mmc1_pins>;
>>>> + max-frequency = <150000000>;
>>>> + status = "okay";
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> + vmmc-supply = <®_vcc33_wifi>;
>>>> + vqmmc-supply = <®_vcc_wifi_io>;
>>>> + mmc-pwrseq = <&wifi_pwrseq>;
>>>> + bus-width = <4>;
>>>> + non-removable;
>>>> +
>>>> + brcm: sdio-wifi@1 {
>>>> + reg = <1>;
>>>> + compatible = "brcm,bcm4329-fmac";
>>>> + interrupt-parent = <&r_pio>;
>>>> + interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */
>>>> + interrupt-names = "host-wake";
>>>> + };
>>>> + };
>>>> +
>>>> + mmc2: mmc@4022000 {
>>>> + compatible = "allwinner,sun50i-h6-emmc";
>>>> + reg = <0x04022000 0x1000>;
>>>> + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
>>>> + clock-names = "ahb", "mmc";
>>>> + resets = <&ccu RST_BUS_MMC2>;
>>>> + reset-names = "ahb";
>>>> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&mmc2_pins>;
>>>> + max-frequency = <150000000>;
>>>> + status = "okay";
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> + vmmc-supply = <®_cldo1>;
>>>> + vqmmc-supply = <®_bldo2>;
>>>> + cap-mmc-hw-reset;
>>>> + non-removable;
>>>> + bus-width = <8>;
>>>> + };
>>>> +
>>>> + uart0: serial@5000000 {
>>>> + compatible = "snps,dw-apb-uart";
>>>> + reg = <0x05000000 0x400>;
>>>> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
>>>> + reg-shift = <2>;
>>>> + reg-io-width = <4>;
>>>> + clocks = <&ccu CLK_BUS_UART0>;
>>>> + resets = <&ccu RST_BUS_UART0>;
>>>> + status = "okay";
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&uart0_ph_pins>;
>>>> + };
>>>> +
>>>> + uart1: serial@5000400 {
>>>> + compatible = "snps,dw-apb-uart";
>>>> + reg = <0x05000400 0x400>;
>>>> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
>>>> + reg-shift = <2>;
>>>> + reg-io-width = <4>;
>>>> + clocks = <&ccu CLK_BUS_UART1>;
>>>> + resets = <&ccu RST_BUS_UART1>;
>>>> + status = "okay";
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
>>>> + uart-has-rtscts;
>>>> +
>>>> + bluetooth {
>>>> + compatible = "brcm,bcm4345c5";
>>>> + clocks = <&rtc 1>;
>>>> + clock-names = "lpo";
>>>> + device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */
>>>> + host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */
>>>> + shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */
>>>> + max-speed = <1500000>;
>>>> + };
>>>> + };
>>>> +
>>>> + uart2: serial@5000800 {
>>>> + compatible = "snps,dw-apb-uart";
>>>> + reg = <0x05000800 0x400>;
>>>> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
>>>> + reg-shift = <2>;
>>>> + reg-io-width = <4>;
>>>> + clocks = <&ccu CLK_BUS_UART2>;
>>>> + resets = <&ccu RST_BUS_UART2>;
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + uart3: serial@5000c00 {
>>>> + compatible = "snps,dw-apb-uart";
>>>> + reg = <0x05000c00 0x400>;
>>>> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
>>>> + reg-shift = <2>;
>>>> + reg-io-width = <4>;
>>>> + clocks = <&ccu CLK_BUS_UART3>;
>>>> + resets = <&ccu RST_BUS_UART3>;
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + i2c0: i2c@5002000 {
>>>> + compatible = "allwinner,sun50i-h6-i2c",
>>>> + "allwinner,sun6i-a31-i2c";
>>>> + reg = <0x05002000 0x400>;
>>>> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&ccu CLK_BUS_I2C0>;
>>>> + resets = <&ccu RST_BUS_I2C0>;
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&i2c0_pins>;
>>>> + status = "disabled";
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> + };
>>>> +
>>>> + i2c1: i2c@5002400 {
>>>> + compatible = "allwinner,sun50i-h6-i2c",
>>>> + "allwinner,sun6i-a31-i2c";
>>>> + reg = <0x05002400 0x400>;
>>>> + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&ccu CLK_BUS_I2C1>;
>>>> + resets = <&ccu RST_BUS_I2C1>;
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&i2c1_pins>;
>>>> + status = "disabled";
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> + };
>>>> +
>>>> + i2c2: i2c@5002800 {
>>>> + compatible = "allwinner,sun50i-h6-i2c",
>>>> + "allwinner,sun6i-a31-i2c";
>>>> + reg = <0x05002800 0x400>;
>>>> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&ccu CLK_BUS_I2C2>;
>>>> + resets = <&ccu RST_BUS_I2C2>;
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&i2c2_pins>;
>>>> + status = "disabled";
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> + };
>>>> +
>>>> + i2c3: i2c@5002c00 {
>>>> + compatible = "allwinner,sun50i-h6-i2c",
>>>> + "allwinner,sun6i-a31-i2c";
>>>> + reg = <0x05002c00 0x400>;
>>>> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&ccu CLK_BUS_I2C3>;
>>>> + resets = <&ccu RST_BUS_I2C3>;
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&i2c3_pins>;
>>>> + clock-frequency = <100000>;
>>>> + status = "okay"; /* нужно для ac200 */
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + ac200: mfd@10 {
>>>> + compatible = "x-powers,ac200";
>>>> + reg = <0x10>;
>>>> + clocks = <&ac200_pwm_clk>;
>>>> + interrupt-parent = <&pio>;
>>>> + interrupts = <1 20 IRQ_TYPE_LEVEL_LOW>;
>>>> + interrupt-controller;
>>>> + #interrupt-cells = <1>;
>>>> + nvmem-cells = <&ac200_bg>;
>>>> + nvmem-cell-names = "bandgap";
>>>> +
>>>> + ac200_ephy_ctl: syscon {
>>>> + compatible = "x-powers,ac200-ephy-ctl";
>>>> + nvmem-cells = <&ephy_calib>;
>>>> + nvmem-cell-names = "calibration";
>>>> + #clock-cells = <0>;
>>>> + #reset-cells = <0>;
>>>> + phy-mode = "rmii";
>>>> + status = "okay";
>>>> + x-powers,led-polarity = <GPIO_ACTIVE_HIGH>;
>>>> + phy-address = <1>;
>>>> + };
>>>> +
>>>> + ac200_codec: codec {
>>>> + #sound-dai-cells = <0>;
>>>> + compatible = "x-powers,ac200-codec";
>>>> + status = "okay";
>>>> + avcc-supply = <®_aldo2>;
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + spi1: spi@5011000 {
>>>> + compatible = "allwinner,sun50i-h6-spi",
>>>> + "allwinner,sun8i-h3-spi";
>>>> + reg = <0x05011000 0x1000>;
>>>> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
>>>> + clock-names = "ahb", "mod";
>>>> + dmas = <&dma 23>, <&dma 23>;
>>>> + dma-names = "rx", "tx";
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&spi1_pins>, <&spi1_cs_pin>;
>>>> + resets = <&ccu RST_BUS_SPI1>;
>>>> + status = "disabled";
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> + };
>>>> +
>>>> + emac: ethernet@5020000 {
>>>> + compatible = "allwinner,sun50i-h6-emac",
>>>> + "allwinner,sun50i-a64-emac";
>>>> + syscon = <&syscon>;
>>>> + reg = <0x05020000 0x10000>;
>>>> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>>>> + interrupt-names = "macirq";
>>>> + resets = <&ccu RST_BUS_EMAC>;
>>>> + reset-names = "stmmaceth";
>>>> + clocks = <&ccu CLK_BUS_EMAC>;
>>>> + clock-names = "stmmaceth";
>>>> + status = "okay";
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&ext_rmii_pins>;
>>>> + phy-mode = "rmii";
>>>> + phy-handle = <&ext_rmii_phy>;
>>>> +
>>>> + mdio: mdio {
>>>> + compatible = "snps,dwmac-mdio";
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + ext_rmii_phy: ethernet-phy@1 {
>>>> + compatible = "ethernet-phy-id0044.1400",
>>>> + "ethernet-phy-ieee802.3-c22";
>>>> + reg = <1>;
>>>> + resets = <&ac200_ephy_ctl>;
>>>> + reset-names = "phy";
>>>> + clocks = <&ac200_ephy_ctl>;
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + i2s3: i2s@508f000 {
>>>> + #sound-dai-cells = <0>;
>>>> + compatible = "allwinner,sun50i-h6-i2s";
>>>> + reg = <0x0508f000 0x1000>;
>>>> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&ccu CLK_BUS_I2S3>, <&ccu CLK_I2S3>;
>>>> + clock-names = "apb", "mod";
>>>> + dmas = <&dma 6>, <&dma 6>;
>>>> + resets = <&ccu RST_BUS_I2S3>;
>>>> + dma-names = "rx", "tx";
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&i2s3_pins>;
>>>> + status = "okay";
>>>> + };
>>>> +
>>>> + i2s2: i2s@5092000 {
>>>> + #sound-dai-cells = <0>;
>>>> + compatible = "allwinner,sun50i-h6-i2s";
>>>> + reg = <0x05092000 0x1000>;
>>>> + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
>>>> + clock-names = "apb", "mod";
>>>> + dmas = <&dma 5>, <&dma 5>;
>>>> + resets = <&ccu RST_BUS_I2S2>;
>>>> + dma-names = "rx", "tx";
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + i2s1: i2s@5091000 {
>>>> + #sound-dai-cells = <0>;
>>>> + compatible = "allwinner,sun50i-h6-i2s";
>>>> + reg = <0x05091000 0x1000>;
>>>> + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
>>>> + clock-names = "apb", "mod";
>>>> + dmas = <&dma 4>, <&dma 4>;
>>>> + resets = <&ccu RST_BUS_I2S1>;
>>>> + dma-names = "rx", "tx";
>>>> + status = "okay";
>>>> + };
>>>> +
>>>> + spdif: spdif@5093000 {
>>>> + #sound-dai-cells = <0>;
>>>> + compatible = "allwinner,sun50i-h6-spdif";
>>>> + reg = <0x05093000 0x400>;
>>>> + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
>>>> + clock-names = "apb", "spdif";
>>>> + resets = <&ccu RST_BUS_SPDIF>;
>>>> + dmas = <&dma 2>, <&dma 2>;
>>>> + dma-names = "rx", "tx";
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + usb2otg: usb@5100000 {
>>>> + compatible = "allwinner,sun50i-h6-musb",
>>>> + "allwinner,sun8i-a33-musb";
>>>> + reg = <0x05100000 0x0400>;
>>>> + clocks = <&ccu CLK_BUS_OTG>;
>>>> + resets = <&ccu RST_BUS_OTG>;
>>>> + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
>>>> + interrupt-names = "mc";
>>>> + phys = <&usb2phy 0>;
>>>> + phy-names = "usb";
>>>> + extcon = <&usb2phy 0>;
>>>> + status = "okay";
>>>> + dr_mode = "host";
>>>> + };
>>>> +
>>>> + usb2phy: phy@5100400 {
>>>> + compatible = "allwinner,sun50i-h6-usb-phy";
>>>> + reg = <0x05100400 0x24>,
>>>> + <0x05101800 0x4>,
>>>> + <0x05311800 0x4>;
>>>> + reg-names = "phy_ctrl",
>>>> + "pmu0",
>>>> + "pmu3";
>>>> + clocks = <&ccu CLK_USB_PHY0>,
>>>> + <&ccu CLK_USB_PHY3>;
>>>> + clock-names = "usb0_phy",
>>>> + "usb3_phy";
>>>> + resets = <&ccu RST_USB_PHY0>,
>>>> + <&ccu RST_USB_PHY3>;
>>>> + reset-names = "usb0_reset",
>>>> + "usb3_reset";
>>>> + status = "okay";
>>>> + #phy-cells = <1>;
>>>> + };
>>>> +
>>>> + ehci0: usb@5101000 {
>>>> + compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
>>>> + reg = <0x05101000 0x100>;
>>>> + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&ccu CLK_BUS_OHCI0>,
>>>> + <&ccu CLK_BUS_EHCI0>,
>>>> + <&ccu CLK_USB_OHCI0>;
>>>> + resets = <&ccu RST_BUS_OHCI0>,
>>>> + <&ccu RST_BUS_EHCI0>;
>>>> + phys = <&usb2phy 0>;
>>>> + phy-names = "usb";
>>>> + status = "okay";
>>>> + };
>>>> +
>>>> + ohci0: usb@5101400 {
>>>> + compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
>>>> + reg = <0x05101400 0x100>;
>>>> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&ccu CLK_BUS_OHCI0>,
>>>> + <&ccu CLK_USB_OHCI0>;
>>>> + resets = <&ccu RST_BUS_OHCI0>;
>>>> + phys = <&usb2phy 0>;
>>>> + phy-names = "usb";
>>>> + status = "okay";
>>>> + };
>>>> +
>>>> + dwc3: usb@5200000 {
>>>> + compatible = "snps,dwc3";
>>>> + reg = <0x05200000 0x10000>;
>>>> + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&ccu CLK_BUS_XHCI>,
>>>> + <&ccu CLK_BUS_XHCI>,
>>>> + <&rtc CLK_OSC32K>;
>>>> + clock-names = "ref", "bus_early", "suspend";
>>>> + resets = <&ccu RST_BUS_XHCI>;
>>>> + /*
>>>> + * The datasheet of the chip doesn't declare the
>>>> + * peripheral function, and there's no boards known
>>>> + * to have a USB Type-B port routed to the port.
>>>> + * In addition, no one has tested the peripheral
>>>> + * function yet.
>>>> + * So set the dr_mode to "host" in the DTSI file.
>>>> + */
>>>> + dr_mode = "host";
>>>> + phys = <&usb3phy>;
>>>> + phy-names = "usb3-phy";
>>>> + status = "okay";
>>>> + };
>>>> +
>>>> + usb3phy: phy@5210000 {
>>>> + compatible = "allwinner,sun50i-h6-usb3-phy";
>>>> + reg = <0x5210000 0x10000>;
>>>> + clocks = <&ccu CLK_USB_PHY1>;
>>>> + resets = <&ccu RST_USB_PHY1>;
>>>> + #phy-cells = <0>;
>>>> + status = "okay";
>>>> + };
>>>> +
>>>> + ehci3: usb@5311000 {
>>>> + compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
>>>> + reg = <0x05311000 0x100>;
>>>> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&ccu CLK_BUS_OHCI3>,
>>>> + <&ccu CLK_BUS_EHCI3>,
>>>> + <&ccu CLK_USB_OHCI3>;
>>>> + resets = <&ccu RST_BUS_OHCI3>,
>>>> + <&ccu RST_BUS_EHCI3>;
>>>> + phys = <&usb2phy 3>;
>>>> + phy-names = "usb";
>>>> + status = "okay";
>>>> + };
>>>> +
>>>> + ohci3: usb@5311400 {
>>>> + compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
>>>> + reg = <0x05311400 0x100>;
>>>> + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&ccu CLK_BUS_OHCI3>,
>>>> + <&ccu CLK_USB_OHCI3>;
>>>> + resets = <&ccu RST_BUS_OHCI3>;
>>>> + phys = <&usb2phy 3>;
>>>> + phy-names = "usb";
>>>> + status = "okay";
>>>> + };
>>>> +
>>>> + pcie: pcie@5400000 {
>>>> + #address-cells = <3>;
>>>> + #size-cells = <2>;
>>>> + compatible = "pine64,allwinner-h6-pcie-wrapped";
>>>> + reg = <0x05400000 0x4000>,
>>>> + <0x05410000 0x10000>;
>>>> + reg-names = "dbi", "config";
>>>> + device_type = "pci";
>>>> + bus-range = <0x00 0xff>;
>>>> + ranges = <0x81000000 0 0 0x05e00000 0 0x00010000 /* downstream I/O */
>>>> + 0x82000000 0 0x05500000 0x05500000 0 0x00800000>; /* non-prefetchable memory */
>>>> + num-lanes = <1>;
>>>> + max-link-speed = <2>;
>>>> + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
>>>> + interrupt-names = "msi", "linkup";
>>>> + clocks = <&ccu CLK_PCIE_REF_OUT>,
>>>> + <&ccu CLK_PCIE_MAXI>,
>>>> + <&ccu CLK_PCIE_AUX>,
>>>> + <&ccu CLK_BUS_PCIE>;
>>>> + clock-names = "ref", "axi", "aux", "bus";
>>>> + resets = <&ccu RST_PCIE_POWERUP>, <&ccu RST_BUS_PCIE>;
>>>> + reset-names = "power", "bus";
>>>> + #interrupt-cells = <1>;
>>>> + interrupt-map-mask = <0 0 0 0>;
>>>> + interrupt-map = <0 0 0 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
>>>> + status = "okay";
>>>> + vcc-supply = <®_bldo2>;
>>>> + vdd-supply = <®_dcdcd>;
>>>> + slot-supply = <®_vcc33_wifi>;
>>>> + perst-gpio = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */
>>>> + /* clkreq-gpio = <&r_pio 0 5 GPIO_ACTIVE_LOW>; */
>>>> + /* wake-gpio = <&r_pio 0 4 0>; */
>>>> + };
>>>> +
>>>> +
>>>> + hdmi: hdmi@6000000 {
>>>> + #sound-dai-cells = <0>;
>>>> + compatible = "allwinner,sun50i-h6-dw-hdmi";
>>>> + reg = <0x06000000 0x10000>;
>>>> + reg-io-width = <1>;
>>>> + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
>>>> + <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
>>>> + <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
>>>> + clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
>>>> + "hdcp-bus";
>>>> + resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
>>>> + reset-names = "ctrl", "hdcp";
>>>> + phys = <&hdmi_phy>;
>>>> + phy-names = "phy";
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&hdmi_pins>;
>>>> + status = "okay";
>>>> +
>>>> + ports {
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + hdmi_in: port@0 {
>>>> + reg = <0>;
>>>> +
>>>> + hdmi_in_tcon_top: endpoint {
>>>> + remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
>>>> + };
>>>> + };
>>>> +
>>>> + hdmi_out: port@1 {
>>>> + reg = <1>;
>>>> +
>>>> + hdmi_out_con: endpoint {
>>>> + remote-endpoint = <&hdmi_con_in>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + hdmi_phy: hdmi-phy@6010000 {
>>>> + compatible = "allwinner,sun50i-h6-hdmi-phy";
>>>> + reg = <0x06010000 0x10000>;
>>>> + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
>>>> + clock-names = "bus", "mod";
>>>> + resets = <&ccu RST_BUS_HDMI>;
>>>> + reset-names = "phy";
>>>> + #phy-cells = <0>;
>>>> + };
>>>> +
>>>> + tcon_top: tcon-top@6510000 {
>>>> + compatible = "allwinner,sun50i-h6-tcon-top";
>>>> + reg = <0x06510000 0x1000>;
>>>> + clocks = <&ccu CLK_BUS_TCON_TOP>,
>>>> + <&ccu CLK_TCON_TV0>;
>>>> + clock-names = "bus",
>>>> + "tcon-tv0";
>>>> + clock-output-names = "tcon-top-tv0";
>>>> + resets = <&ccu RST_BUS_TCON_TOP>;
>>>> + #clock-cells = <1>;
>>>> +
>>>> + ports {
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + tcon_top_mixer0_in: port@0 {
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> + reg = <0>;
>>>> +
>>>> + tcon_top_mixer0_in_mixer0: endpoint@0 {
>>>> + reg = <0>;
>>>> + remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
>>>> + };
>>>> + };
>>>> +
>>>> + tcon_top_mixer0_out: port@1 {
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> + reg = <1>;
>>>> +
>>>> + tcon_top_mixer0_out_tcon_tv: endpoint@2 {
>>>> + reg = <2>;
>>>> + remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
>>>> + };
>>>> + };
>>>> +
>>>> + tcon_top_hdmi_in: port@4 {
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> + reg = <4>;
>>>> +
>>>> + tcon_top_hdmi_in_tcon_tv: endpoint@0 {
>>>> + reg = <0>;
>>>> + remote-endpoint = <&tcon_tv_out_tcon_top>;
>>>> + };
>>>> + };
>>>> +
>>>> + tcon_top_hdmi_out: port@5 {
>>>> + reg = <5>;
>>>> +
>>>> + tcon_top_hdmi_out_hdmi: endpoint {
>>>> + remote-endpoint = <&hdmi_in_tcon_top>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + tcon_tv: lcd-controller@6515000 {
>>>> + compatible = "allwinner,sun50i-h6-tcon-tv",
>>>> + "allwinner,sun8i-r40-tcon-tv";
>>>> + reg = <0x06515000 0x1000>;
>>>> + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&ccu CLK_BUS_TCON_TV0>,
>>>> + <&tcon_top CLK_TCON_TOP_TV0>;
>>>> + clock-names = "ahb",
>>>> + "tcon-ch1";
>>>> + resets = <&ccu RST_BUS_TCON_TV0>;
>>>> + reset-names = "lcd";
>>>> +
>>>> + ports {
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + tcon_tv_in: port@0 {
>>>> + reg = <0>;
>>>> +
>>>> + tcon_tv_in_tcon_top_mixer0: endpoint {
>>>> + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
>>>> + };
>>>> + };
>>>> +
>>>> + tcon_tv_out: port@1 {
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> + reg = <1>;
>>>> +
>>>> + tcon_tv_out_tcon_top: endpoint@1 {
>>>> + reg = <1>;
>>>> + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + r_uart: serial@7080000 {
>>>> + compatible = "snps,dw-apb-uart";
>>>> + reg = <0x07080000 0x400>;
>>>> + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
>>>> + reg-shift = <2>;
>>>> + reg-io-width = <4>;
>>>> + clocks = <&r_ccu CLK_R_APB2_UART>;
>>>> + resets = <&r_ccu RST_R_APB2_UART>;
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&r_uart_pins>;
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + rtc: rtc@7000000 {
>>>> + compatible = "allwinner,sun50i-h6-rtc";
>>>> + reg = <0x07000000 0x400>;
>>>> + interrupt-parent = <&r_intc>;
>>>> + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clock-output-names = "osc32k", "osc32k-out", "iosc";
>>>> + #clock-cells = <1>;
>>>> + clocks = <&ext_osc32k>;
>>>> + };
>>>> +
>>>> + r_ccu: clock@7010000 {
>>>> + compatible = "allwinner,sun50i-h6-r-ccu";
>>>> + reg = <0x07010000 0x400>;
>>>> + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
>>>> + <&ccu CLK_PLL_PERIPH0>;
>>>> + clock-names = "hosc", "losc", "iosc", "pll-periph";
>>>> + protected-clocks = <CLK_R_APB1_TWD>;
>>>> + #clock-cells = <1>;
>>>> + #reset-cells = <1>;
>>>> + };
>>>> +
>>>> + r_watchdog: watchdog@7020400 {
>>>> + compatible = "allwinner,sun50i-h6-wdt",
>>>> + "allwinner,sun6i-a31-wdt";
>>>> + reg = <0x07020400 0x20>;
>>>> + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&osc24M>;
>>>> + };
>>>> +
>>>> + r_intc: interrupt-controller@7021000 {
>>>> + compatible = "allwinner,sun50i-h6-r-intc";
>>>> + interrupt-controller;
>>>> + #interrupt-cells = <3>;
>>>> + reg = <0x07021000 0x400>;
>>>> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>> + };
>>>> +
>>>> + r_pwm: pwm@7020C00 {
>>>> + compatible = "allwinner,sun50i-h6-pwm";
>>>> + reg = <0x07020C00 0x400>;
>>>> + clocks = <&osc24M>, <&ccu CLK_R_APB1_PWM>;
>>>> + clock-names = "mod", "bus";
>>>> + resets = <&ccu RST_R_APB1_PWM>;
>>>> + #pwm-cells = <3>;
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + r_pio: pinctrl@7022000 {
>>>> + compatible = "allwinner,sun50i-h6-r-pinctrl";
>>>> + reg = <0x07022000 0x400>;
>>>> + interrupt-parent = <&r_intc>;
>>>> + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&r_ccu CLK_R_APB1>, <&osc24M>,
>>>> + <&rtc CLK_OSC32K>;
>>>> + clock-names = "apb", "hosc", "losc";
>>>> + gpio-controller;
>>>> + #gpio-cells = <3>;
>>>> + interrupt-controller;
>>>> + #interrupt-cells = <3>;
>>>> +
>>>> + r_i2c_pins: r-i2c-pins {
>>>> + pins = "PL0", "PL1";
>>>> + function = "s_i2c";
>>>> + };
>>>> +
>>>> + r_ir_rx_pin: r-ir-rx-pin {
>>>> + pins = "PL9";
>>>> + function = "s_cir_rx";
>>>> + };
>>>> +
>>>> + r_rsb_pins: r-rsb-pins {
>>>> + pins = "PL0", "PL1";
>>>> + function = "s_rsb";
>>>> + };
>>>> +
>>>> + r_uart_pins: r-uart-pins {
>>>> + pins = "PL2", "PL3";
>>>> + function = "s_uart";
>>>> + };
>>>> +
>>>> + r_pwm_pin: r-pwm-pin {
>>>> + pins = "PL8";
>>>> + function = "s_pwm";
>>>> + };
>>>> +
>>>> + };
>>>> +
>>>> + r_ir: ir@7040000 {
>>>> + compatible = "allwinner,sun50i-h6-ir",
>>>> + "allwinner,sun6i-a31-ir";
>>>> + reg = <0x07040000 0x400>;
>>>> + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&r_ccu CLK_R_APB1_IR>,
>>>> + <&r_ccu CLK_IR>;
>>>> + clock-names = "apb", "ir";
>>>> + resets = <&r_ccu RST_R_APB1_IR>;
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&r_ir_rx_pin>;
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + r_i2c: i2c@7081400 {
>>>> + compatible = "allwinner,sun50i-h6-i2c",
>>>> + "allwinner,sun6i-a31-i2c";
>>>> + reg = <0x07081400 0x400>;
>>>> + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&r_ccu CLK_R_APB2_I2C>;
>>>> + resets = <&r_ccu RST_R_APB2_I2C>;
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&r_i2c_pins>;
>>>> + status = "okay";
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + axp805: pmic@36 {
>>>> + compatible = "x-powers,axp805", "x-powers,axp806";
>>>> + reg = <0x36>;
>>>> + interrupt-parent = <&r_intc>;
>>>> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
>>>> + interrupt-controller;
>>>> + #interrupt-cells = <1>;
>>>> + x-powers,self-working-mode;
>>>> + vina-supply = <®_vcc5v>;
>>>> + vinb-supply = <®_vcc5v>;
>>>> + vinc-supply = <®_vcc5v>;
>>>> + vind-supply = <®_vcc5v>;
>>>> + vine-supply = <®_vcc5v>;
>>>> + aldoin-supply = <®_vcc5v>;
>>>> + bldoin-supply = <®_vcc5v>;
>>>> + cldoin-supply = <®_vcc5v>;
>>>> +
>>>> + regulators {
>>>> + reg_aldo1: aldo1 {
>>>> + regulator-always-on;
>>>> + regulator-min-microvolt = <3300000>;
>>>> + regulator-max-microvolt = <3300000>;
>>>> + regulator-name = "vcc-pl-led-ir";
>>>> + };
>>>> +
>>>> + reg_aldo2: aldo2 {
>>>> + regulator-always-on;
>>>> + regulator-min-microvolt = <3300000>;
>>>> + regulator-max-microvolt = <3300000>;
>>>> + regulator-name = "vcc33-audio-tv-ephy-mac";
>>>> + regulator-enable-ramp-delay = <100000>;
>>>> + };
>>>> +
>>>> + reg_aldo3: aldo3 {
>>>> + regulator-always-on;
>>>> + regulator-min-microvolt = <3300000>;
>>>> + regulator-max-microvolt = <3300000>;
>>>> + regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-1";
>>>> + };
>>>> +
>>>> + reg_bldo1: bldo1 {
>>>> + regulator-always-on;
>>>> + regulator-min-microvolt = <1800000>;
>>>> + regulator-max-microvolt = <1800000>;
>>>> + regulator-name = "vcc18-dram-bias-pll";
>>>> + };
>>>> +
>>>> + reg_bldo2: bldo2 {
>>>> + regulator-always-on;
>>>> + regulator-min-microvolt = <1800000>;
>>>> + regulator-max-microvolt = <1800000>;
>>>> + regulator-name = "vcc-efuse-pcie-hdmi-pc";
>>>> + };
>>>> +
>>>> + reg_bldo3: bldo3 {
>>>> + regulator-always-on;
>>>> + regulator-min-microvolt = <1800000>;
>>>> + regulator-max-microvolt = <1800000>;
>>>> + regulator-name = "vcc-dcxoio";
>>>> + };
>>>> +
>>>> + reg_bldo4: bldo4 {
>>>> + regulator-always-on;
>>>> + regulator-min-microvolt = <1800000>;
>>>> + regulator-max-microvolt = <1800000>;
>>>> + regulator-name = "vcc-dcxoio";
>>>> + };
>>>> +
>>>> + reg_cldo1: cldo1 {
>>>> + regulator-always-on;
>>>> + regulator-min-microvolt = <3300000>;
>>>> + regulator-max-microvolt = <3300000>;
>>>> + regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2";
>>>> + };
>>>> +
>>>> + reg_cldo2: cldo2 {
>>>> + regulator-min-microvolt = <3300000>;
>>>> + regulator-max-microvolt = <3300000>;
>>>> + regulator-name = "vcc-wifi-1";
>>>> + };
>>>> +
>>>> + reg_cldo3: cldo3 {
>>>> + regulator-min-microvolt = <3300000>;
>>>> + regulator-max-microvolt = <3300000>;
>>>> + regulator-name = "vcc-wifi-2";
>>>> + };
>>>> +
>>>> + reg_dcdca: dcdca {
>>>> + regulator-always-on;
>>>> + regulator-min-microvolt = <810000>;
>>>> + regulator-max-microvolt = <1200000>;
>>>> + regulator-ramp-delay = <2500>;
>>>> + regulator-name = "vdd-cpu";
>>>> + };
>>>> +
>>>> + reg_dcdcc: dcdcc {
>>>> + regulator-enable-ramp-delay = <32000>;
>>>> + regulator-min-microvolt = <810000>;
>>>> + regulator-max-microvolt = <1080000>;
>>>> + regulator-ramp-delay = <2500>;
>>>> + regulator-name = "vdd-gpu";
>>>> + };
>>>> +
>>>> + reg_dcdcd: dcdcd {
>>>> + regulator-always-on;
>>>> + regulator-min-microvolt = <1000000>;
>>>> + regulator-max-microvolt = <1000000>;
>>>> + regulator-name = "vdd-sys";
>>>> + };
>>>> +
>>>> + sw {
>>>> + /* unused */
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + r_rsb: rsb@7083000 {
>>>> + compatible = "allwinner,sun8i-a23-rsb";
>>>> + reg = <0x07083000 0x400>;
>>>> + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&r_ccu CLK_R_APB2_RSB>;
>>>> + clock-frequency = <3000000>;
>>>> + resets = <&r_ccu RST_R_APB2_RSB>;
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&r_rsb_pins>;
>>>> + status = "disabled";
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> + };
>>>> +
>>>> + ths: thermal-sensor@5070400 {
>>>> + compatible = "allwinner,sun50i-h6-ths";
>>>> + reg = <0x05070400 0x100>;
>>>> + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&ccu CLK_BUS_THS>;
>>>> + clock-names = "bus";
>>>> + resets = <&ccu RST_BUS_THS>;
>>>> + nvmem-cells = <&ths_calibration>;
>>>> + nvmem-cell-names = "calibration";
>>>> + #thermal-sensor-cells = <1>;
>>>> + };
>>>> +
>>>> + sunxi-info {
>>>> + compatible = "allwinner,sun50i-h6-sys-info";
>>>> + status = "okay";
>>>> + };
>>>> +
>>>> + addr_mgt: addr-mgt {
>>>> + compatible = "allwinner,sunxi-addr_mgt";
>>>> + type_addr_wifi = <0x2>;
>>>> + type_addr_bt = <0x2>;
>>>> + type_addr_eth = <0x2>;
>>>> + status = "okay";
>>>> + };
>>>> +
>>>> + dump_reg: dump_reg@20000 {
>>>> + compatible = "allwinner,sunxi-dump-reg";
>>>> + reg = <0x0 0x03001000 0x0 0x0f20>;
>>>> + status = "okay";
>>>> + };
>>>> + };
>>>> +
>>>> + thermal-zones {
>>>> + cpu-thermal {
>>>> + polling-delay-passive = <250>;
>>>> + polling-delay = <1000>;
>>>> + thermal-sensors = <&ths 0>;
>>>> +
>>>> + trips {
>>>> + cpu_warm: cpu_warm {
>>>> + temperature = <70000>;
>>>> + hysteresis = <2000>;
>>>> + type = "passive";
>>>> + };
>>>> +
>>>> + cpu_hot0: cpu_hot0 {
>>>> + temperature = <74000>;
>>>> + hysteresis = <2000>;
>>>> + type = "passive";
>>>> + };
>>>> +
>>>> + cpu_hot1: cpu_hot1 {
>>>> + temperature = <76000>;
>>>> + hysteresis = <2000>;
>>>> + type = "passive";
>>>> + };
>>>> +
>>>> + cpu_very_hot0: cpu_very_hot0 {
>>>> + temperature = <78000>;
>>>> + hysteresis = <2000>;
>>>> + type = "passive";
>>>> + };
>>>> +
>>>> + cpu_very_hot1: cpu_very_hot1 {
>>>> + temperature = <80000>;
>>>> + hysteresis = <2000>;
>>>> + type = "passive";
>>>> + };
>>>> +
>>>> + cpu_very_hot2: cpu_very_hot2 {
>>>> + temperature = <82000>;
>>>> + hysteresis = <2000>;
>>>> + type = "passive";
>>>> + };
>>>> +
>>>> + cpu_very_hot3: cpu_very_hot3 {
>>>> + temperature = <84000>;
>>>> + hysteresis = <2000>;
>>>> + type = "passive";
>>>> + };
>>>> +
>>>> + cpu_very_hot4: cpu_very_hot4 {
>>>> + temperature = <86000>;
>>>> + hysteresis = <2000>;
>>>> + type = "passive";
>>>> + };
>>>> +
>>>> + cpu_very_hot5: cpu_very_hot5 {
>>>> + temperature = <88000>;
>>>> + hysteresis = <2000>;
>>>> + type = "passive";
>>>> + };
>>>> +
>>>> + cpu_very_hot6: cpu_very_hot6 {
>>>> + temperature = <90000>;
>>>> + hysteresis = <2000>;
>>>> + type = "passive";
>>>> + };
>>>> +
>>>> + cpu_crit: cpu_crit {
>>>> + temperature = <97000>;
>>>> + hysteresis = <2000>;
>>>> + type = "critical";
>>>> + };
>>>> + };
>>>> +
>>>> + cooling-maps {
>>>> + cpu_warm_limit_cpu {
>>>> + trip = <&cpu_warm>;
>>>> + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + gpu-thermal {
>>>> + polling-delay-passive = <1000>;
>>>> + polling-delay = <2000>;
>>>> + thermal-sensors = <&ths 1>;
>>>> +
>>>> + trips {
>>>> + gpu_alert0: gpu-alert-0 {
>>>> + temperature = <95000>;
>>>> + hysteresis = <2000>;
>>>> + type = "passive";
>>>> + };
>>>> +
>>>> + gpu_alert1: gpu-alert-1 {
>>>> + temperature = <100000>;
>>>> + hysteresis = <2000>;
>>>> + type = "passive";
>>>> + };
>>>> +
>>>> + gpu_alert2: gpu-alert-2 {
>>>> + temperature = <105000>;
>>>> + hysteresis = <2000>;
>>>> + type = "passive";
>>>> + };
>>>> +
>>>> + gpu-crit {
>>>> + temperature = <115000>;
>>>> + hysteresis = <0>;
>>>> + type = "critical";
>>>> + };
>>>> + };
>>>> +
>>>> + cooling-maps {
>>>> + // Forbid the GPU to go over 756MHz
>>>> + map0 {
>>>> + trip = <&gpu_alert0>;
>>>> + cooling-device = <&gpu 1 THERMAL_NO_LIMIT>;
>>>> + };
>>>> +
>>>> + // Forbid the GPU to go over 624MHz
>>>> + map1 {
>>>> + trip = <&gpu_alert1>;
>>>> + cooling-device = <&gpu 2 THERMAL_NO_LIMIT>;
>>>> + };
>>>> +
>>>> + // Forbid the GPU to go over 576MHz
>>>> + map2 {
>>>> + trip = <&gpu_alert2>;
>>>> + cooling-device = <&gpu 3 THERMAL_NO_LIMIT>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + cpu_opp_table: cpu-opp-table {
>>>> + compatible = "allwinner,sun50i-h6-operating-points";
>>>> + nvmem-cells = <&cpu_speed_grade>;
>>>> + opp-shared;
>>>> +
>>>> + opp-480000000 {
>>>> + clock-latency-ns = <244144>; /* 8 32k periods */
>>>> + opp-hz = /bits/ 64 <480000000>;
>>>> +
>>>> + opp-microvolt-speed0 = <880000>;
>>>> + };
>>>> +
>>>> + opp-720000000 {
>>>> + clock-latency-ns = <244144>; /* 8 32k periods */
>>>> + opp-hz = /bits/ 64 <720000000>;
>>>> +
>>>> + opp-microvolt-speed0 = <880000>;
>>>> + };
>>>> +
>>>> + opp-888000000 {
>>>> + clock-latency-ns = <244144>; /* 8 32k periods */
>>>> + opp-hz = /bits/ 64 <888000000>;
>>>> +
>>>> + opp-microvolt-speed0 = <880000>;
>>>> + };
>>>> +
>>>> + opp-1080000000 {
>>>> + clock-latency-ns = <244144>; /* 8 32k periods */
>>>> + opp-hz = /bits/ 64 <1080000000>;
>>>> +
>>>> + opp-microvolt-speed0 = <940000>;
>>>> + };
>>>> +
>>>> + opp-1320000000 {
>>>> + clock-latency-ns = <244144>; /* 8 32k periods */
>>>> + opp-hz = /bits/ 64 <1320000000>;
>>>> +
>>>> + opp-microvolt-speed0 = <1000000>;
>>>> + };
>>>> +
>>>> + opp-1488000000 {
>>>> + clock-latency-ns = <244144>; /* 8 32k periods */
>>>> + opp-hz = /bits/ 64 <1488000000>;
>>>> +
>>>> + opp-microvolt-speed0 = <1060000>;
>>>> + };
>>>> +
>>>> + opp-1608000000 {
>>>> + clock-latency-ns = <244144>; /* 8 32k periods */
>>>> + opp-hz = /bits/ 64 <1608000000>;
>>>> +
>>>> + opp-microvolt-speed0 = <1090000>;
>>>> + };
>>>> +
>>>> + opp-1704000000 {
>>>> + clock-latency-ns = <244144>; /* 8 32k periods */
>>>> + opp-hz = /bits/ 64 <1704000000>;
>>>> +
>>>> + opp-microvolt-speed0 = <1120000>;
>>>> + };
>>>> +
>>>> + opp-1800000000 {
>>>> + clock-latency-ns = <244144>; /* 8 32k periods */
>>>> + opp-hz = /bits/ 64 <1800000000>;
>>>> +
>>>> + opp-microvolt-speed0 = <1160000>;
>>>> + };
>>>> +
>>>> + opp@1896000000 {
>>>> + clock-latency-ns = <244144>; /* 8 32k periods */
>>>> + opp-hz = /bits/ 64 <1896000000>;
>>>> +
>>>> + opp-microvolt-speed0 = <1180000>;
>>>> + };
>>>> +
>>>> + opp@1968000000 {
>>>> + clock-latency-ns = <244144>; /* 8 32k periods */
>>>> + opp-hz = /bits/ 64 <1968000000>;
>>>> +
>>>> + opp-microvolt-speed0 = <1200000>;
>>>> + };
>>>> +
>>>> + };
>>>> +
>>>> + gpu_opp_table: opp-table-gpu {
>>>> + compatible = "operating-points-v2";
>>>> +
>>>> + opp-216000000 {
>>>> + opp-hz = /bits/ 64 <216000000>;
>>>> + opp-microvolt = <810000 810000 1200000>;
>>>> + };
>>>> +
>>>> + opp-264000000 {
>>>> + opp-hz = /bits/ 64 <264000000>;
>>>> + opp-microvolt = <810000 810000 1200000>;
>>>> + };
>>>> +
>>>> + opp-312000000 {
>>>> + opp-hz = /bits/ 64 <312000000>;
>>>> + opp-microvolt = <810000 810000 1200000>;
>>>> + };
>>>> +
>>>> + opp-336000000 {
>>>> + opp-hz = /bits/ 64 <336000000>;
>>>> + opp-microvolt = <810000 810000 1200000>;
>>>> + };
>>>> +
>>>> + opp-360000000 {
>>>> + opp-hz = /bits/ 64 <360000000>;
>>>> + opp-microvolt = <820000 820000 1200000>;
>>>> + };
>>>> +
>>>> + opp-384000000 {
>>>> + opp-hz = /bits/ 64 <384000000>;
>>>> + opp-microvolt = <830000 830000 1200000>;
>>>> + };
>>>> +
>>>> + opp-408000000 {
>>>> + opp-hz = /bits/ 64 <408000000>;
>>>> + opp-microvolt = <840000 840000 1200000>;
>>>> + };
>>>> +
>>>> + opp-420000000 {
>>>> + opp-hz = /bits/ 64 <420000000>;
>>>> + opp-microvolt = <850000 850000 1200000>;
>>>> + };
>>>> +
>>>> + opp-432000000 {
>>>> + opp-hz = /bits/ 64 <432000000>;
>>>> + opp-microvolt = <860000 860000 1200000>;
>>>> + };
>>>> +
>>>> + opp-456000000 {
>>>> + opp-hz = /bits/ 64 <456000000>;
>>>> + opp-microvolt = <870000 870000 1200000>;
>>>> + };
>>>> +
>>>> + opp-504000000 {
>>>> + opp-hz = /bits/ 64 <504000000>;
>>>> + opp-microvolt = <890000 890000 1200000>;
>>>> + };
>>>> +
>>>> + opp-540000000 {
>>>> + opp-hz = /bits/ 64 <540000000>;
>>>> + opp-microvolt = <910000 910000 1200000>;
>>>> + };
>>>> +
>>>> + opp-576000000 {
>>>> + opp-hz = /bits/ 64 <576000000>;
>>>> + opp-microvolt = <930000 930000 1200000>;
>>>> + };
>>>> +
>>>> + opp-624000000 {
>>>> + opp-hz = /bits/ 64 <624000000>;
>>>> + opp-microvolt = <950000 950000 1200000>;
>>>> + };
>>>> +
>>>> + opp-756000000 {
>>>> + opp-hz = /bits/ 64 <756000000>;
>>>> + opp-microvolt = <1040000 1040000 1200000>;
>>>> + };
>>>> + };
>>>> +
>>>> + chosen {
>>>> + stdout-path = "serial0:115200n8";
>>>> + };
>>>> +
>>>> + connector {
>>>> + compatible = "hdmi-connector";
>>>> + type = "a";
>>>> +
>>>> + port {
>>>> + hdmi_con_in: endpoint {
>>>> + remote-endpoint = <&hdmi_out_con>;
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + ext_osc32k: ext_osc32k_clk {
>>>> + #clock-cells = <0>;
>>>> + compatible = "fixed-clock";
>>>> + clock-frequency = <32768>;
>>>> + clock-output-names = "ext_osc32k";
>>>> + };
>>>> +
>>>> + leds {
>>>> + compatible = "gpio-leds";
>>>> +
>>>> + led-0 {
>>>> + label = "repka:red:power";
>>>> + gpios = <&r_pio 0 9 GPIO_ACTIVE_LOW>; /* PL9 */
>>>> + linux,default-trigger = "heartbeat";
>>>> + };
>>>> + };
>>>> +
>>>> + reg_vcc5v: vcc5v {
>>>> + /* board wide 5V supply directly from the DC jack */
>>>> + compatible = "regulator-fixed";
>>>> + regulator-name = "vcc-5v";
>>>> + regulator-min-microvolt = <5000000>;
>>>> + regulator-max-microvolt = <5000000>;
>>>> + regulator-always-on;
>>>> + };
>>>> +
>>>> + reg_vcc33_wifi: vcc33-wifi {
>>>> + /* Always on 3.3V regulator for WiFi and BT */
>>>> + compatible = "regulator-fixed";
>>>> + regulator-name = "vcc33-wifi";
>>>> + regulator-min-microvolt = <3300000>;
>>>> + regulator-max-microvolt = <3300000>;
>>>> + regulator-always-on;
>>>> + vin-supply = <®_vcc5v>;
>>>> + };
>>>> +
>>>> + reg_vcc_wifi_io: vcc-wifi-io {
>>>> + /* Always on 1.8V/300mA regulator for WiFi and BT IO */
>>>> + compatible = "regulator-fixed";
>>>> + regulator-name = "vcc-wifi-io";
>>>> + regulator-min-microvolt = <1800000>;
>>>> + regulator-max-microvolt = <1800000>;
>>>> + regulator-always-on;
>>>> + vin-supply = <®_vcc33_wifi>;
>>>> + };
>>>> +
>>>> + wifi_pwrseq: wifi-pwrseq {
>>>> + compatible = "mmc-pwrseq-simple";
>>>> + clocks = <&rtc 1>;
>>>> + clock-names = "ext_clock";
>>>> + reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
>>>> + post-power-on-delay-ms = <200>;
>>>> + };
>>>> +};
>>>> --
>>>> 2.42.2
>>>>
>>>> _______________________________________________
>>>> devel-kernel mailing list
>>>> devel-kernel@lists.altlinux.org
>>>> https://lists.altlinux.org/mailman/listinfo/devel-kernel
>>> _______________________________________________
>>> devel-kernel mailing list
>>> devel-kernel@lists.altlinux.org
>>> https://lists.altlinux.org/mailman/listinfo/devel-kernel
>>
>> --
>> Kind Regards!
>> from srebrov@altlinux.org
>>
>> _______________________________________________
>> devel-kernel mailing list
>> devel-kernel@lists.altlinux.org
>> https://lists.altlinux.org/mailman/listinfo/devel-kernel
> _______________________________________________
> devel-kernel mailing list
> devel-kernel@lists.altlinux.org
> https://lists.altlinux.org/mailman/listinfo/devel-kernel
--
best regards, Anton Midyukov <antohami@altlinux.org>
next prev parent reply other threads:[~2025-05-08 1:10 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-06 12:28 kurachenko-urup
2025-05-07 19:39 ` Vitaly Chikunov
2025-05-07 20:50 ` Kurachenko Anton
2025-05-08 0:54 ` Vitaly Chikunov
2025-05-08 1:10 ` Anton Midyukov [this message]
2025-05-08 1:19 ` Vitaly Chikunov
2025-05-08 1:22 ` Vitaly Chikunov
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