[d-kernel] [PATCH 7/7] arm64: dts: rk3588-thin_88rk-1a: enable second hdmi output

[Daniil Gnusarev <gnusarevda@basealt.ru>]

Enable HDMI1 output in dts for the thin_88rk-1a board

Signed-off-by: Daniil Gnusarev <gnusarevda@basealt.ru>
---
 .../edelweiss/rk3588-thin_88rk-1a-common.dtsi | 56 +++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/arch/arm64/boot/dts/edelweiss/rk3588-thin_88rk-1a-common.dtsi b/arch/arm64/boot/dts/edelweiss/rk3588-thin_88rk-1a-common.dtsi
index c34f31de6f2e7..447faa2b638de 100644
--- a/arch/arm64/boot/dts/edelweiss/rk3588-thin_88rk-1a-common.dtsi
+++ b/arch/arm64/boot/dts/edelweiss/rk3588-thin_88rk-1a-common.dtsi
@@ -117,6 +117,17 @@ hdmi0_con_in: endpoint {
 		};
 	};
 
+	hdmi1-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi1_con_in: endpoint {
+				remote-endpoint = <&hdmi1_out_con>;
+			};
+		};
+	};
+
 	vcc_12v0_pcie3x4: regulator-vcc-12v0-pcie3x4 {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc_12v0_pcie3x4";
@@ -501,6 +512,24 @@ &gmac0_rgmii_clk
 };
 
 &vop {
+	clocks = <&cru ACLK_VOP>,
+		 <&cru HCLK_VOP>,
+		 <&cru DCLK_VOP0>,
+		 <&cru DCLK_VOP1>,
+		 <&cru DCLK_VOP2>,
+		 <&cru DCLK_VOP3>,
+		 <&cru PCLK_VOP_ROOT>,
+		 <&hdptxphy_hdmi0>,
+		 <&hdptxphy1>;
+	clock-names = "aclk",
+		      "hclk",
+		      "dclk_vp0",
+		      "dclk_vp1",
+		      "dclk_vp2",
+		      "dclk_vp3",
+		      "pclk_vop",
+		      "pll_hdmiphy0",
+		      "pll_hdmiphy1";
 	status = "okay";
 };
 
@@ -515,6 +544,13 @@ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
 	};
 };
 
+&vp1 {
+	vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI1>;
+		remote-endpoint = <&hdmi1_in_vp1>;
+	};
+};
+
 &hdmi0 {
 	pinctrl-0 = <&hdmim0_tx0_hpd &hdmim2_tx0_scl &hdmim2_tx0_sda>;
 	status = "okay";
@@ -532,10 +568,30 @@ hdmi0_out_con: endpoint {
 	};
 };
 
+&hdmi1 {
+	status = "okay";
+};
+
+&hdmi1_in {
+	hdmi1_in_vp1: endpoint {
+		remote-endpoint = <&vp1_out_hdmi1>;
+	};
+};
+
+&hdmi1_out {
+	hdmi1_out_con: endpoint {
+		remote-endpoint = <&hdmi1_con_in>;
+	};
+};
+
 &hdptxphy_hdmi0 {
 	status = "okay";
 };
 
+&hdptxphy1 {
+	status = "okay";
+};
+
 &spi2 {
 	assigned-clocks = <&cru CLK_SPI2>;
 	assigned-clock-rates = <200000000>;
-- 
2.42.2