From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.1 (2015-04-28) on sa.local.altlinux.org X-Spam-Level: X-Spam-Status: No, score=-3.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RP_MATCHES_RCVD autolearn=ham autolearn_force=no version=3.4.1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=basealt.ru; s=dkim; t=1770799302; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=M1QbEUspYrovvnTXMIKVkmKwJP7bJWd8V1jHCITfKEE=; b=NUwttV102j84O47yxpviD6iOzWDSlMpK1/SIYA0Zbd23Y11bYZS15Du9Zl1/6k0SiXgNVv P23dceLqG4f3NnefhpG4P5mtHAHhsieFJ+Q6d7Y48BISD6ydjc/dyA+ROj/vyp2Ky8iTOX 4mruVREm2YmBiVsqcuXNCT7bHm/tek5LQQYLkJrcDpLkI+heBMsL3dzN6IJoBIRldiFkhG hwe+SP2bmlGbn+Nzt3I/j9/koHYhkuzwN2bGbOfPC1LujsgwlCefohJ7M9nXfLXEBuDA88 Gt/StHbCmXEoqCrzbM7JsvgaN8oXJlOqGoNqyPPwB8HDDA0u8fbqRgRPD22WsQ== From: Daniil Gnusarev To: gnusarevda@basealt.ru, devel-kernel@lists.altlinux.org Date: Wed, 11 Feb 2026 12:41:18 +0400 Message-ID: <20260211084122.353558-7-gnusarevda@basealt.ru> X-Mailer: git-send-email 2.42.2 In-Reply-To: <20260211084122.353558-1-gnusarevda@basealt.ru> References: <20260211084122.353558-1-gnusarevda@basealt.ru> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [d-kernel] [PATCH 6/7] drm/rockchip: vop2: Improve display modes handling on RK3588 HDMI1 X-BeenThere: devel-kernel@lists.altlinux.org X-Mailman-Version: 2.1.12 Precedence: list Reply-To: ALT Linux kernel packages development List-Id: ALT Linux kernel packages development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Feb 2026 08:41:47 -0000 Archived-At: List-Archive: List-Post: From: Cristian Ciocaltea The RK3588 specific implementation is currently quite limited in terms of handling the full range of display modes supported by the connected screens, e.g. 2560x1440@75Hz, 2048x1152@60Hz, 1024x768@60Hz are just a few of them. Additionally, it doesn't cope well with non-integer refresh rates like 59.94, 29.97, 23.98, etc. Make use of HDMI1 PHY PLL as a more accurate DCLK source to handle all display modes up to 4K@60Hz. Signed-off-by: Cristian Ciocaltea Signed-off-by: Heiko Stuebner Link: https://patchwork.freedesktop.org/patch/msgid/20250223-vop2-hdmi1-disp-modes-v2-1-f4cec5e06fbe@collabora.com (cherry picked from commit f8dd7fc9ba88bc4a6ea85269287a51fb756440e2) Signed-off-by: Daniil Gnusarev --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 25 +++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index a551458ad4340..221b8e47f4f8b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -213,6 +213,7 @@ struct vop2 { struct clk *aclk; struct clk *pclk; struct clk *pll_hdmiphy0; + struct clk *pll_hdmiphy1; /* optional internal rgb encoder */ struct rockchip_rgb *rgb; @@ -2082,11 +2083,14 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, * Switch to HDMI PHY PLL as DCLK source for display modes up * to 4K@60Hz, if available, otherwise keep using the system CRU. */ - if (vop2->pll_hdmiphy0 && clock <= VOP2_MAX_DCLK_RATE) { + if ((vop2->pll_hdmiphy0 || vop2->pll_hdmiphy1) && clock <= VOP2_MAX_DCLK_RATE) { drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI0) { + if (!vop2->pll_hdmiphy0) + break; + if (!vp->dclk_src) vp->dclk_src = clk_get_parent(vp->dclk); @@ -2096,6 +2100,20 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, "Could not switch to HDMI0 PHY PLL: %d\n", ret); break; } + + if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI1) { + if (!vop2->pll_hdmiphy1) + break; + + if (!vp->dclk_src) + vp->dclk_src = clk_get_parent(vp->dclk); + + ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy1); + if (ret < 0) + drm_warn(vop2->drm, + "Could not switch to HDMI1 PHY PLL: %d\n", ret); + break; + } } } @@ -3276,6 +3294,11 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) return PTR_ERR(vop2->pll_hdmiphy0); } + vop2->pll_hdmiphy1 = devm_clk_get_optional(vop2->dev, "pll_hdmiphy1"); + if (IS_ERR(vop2->pll_hdmiphy1)) + return dev_err_probe(drm->dev, PTR_ERR(vop2->pll_hdmiphy1), + "failed to get pll_hdmiphy1\n"); + vop2->irq = platform_get_irq(pdev, 0); if (vop2->irq < 0) { drm_err(vop2->drm, "cannot find irq for vop2\n"); -- 2.42.2