From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.1 (2015-04-28) on sa.local.altlinux.org X-Spam-Level: X-Spam-Status: No, score=-3.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RP_MATCHES_RCVD autolearn=ham autolearn_force=no version=3.4.1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=basealt.ru; s=dkim; t=1770799302; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=c26CSY9uHLZfAbtkRlvH/7B609Kn683SNyN22L09W4A=; b=oIT34qrzSTm/2jx9vAKtXQMVL86KDH0exhnq6UJH874SW/s9yLa/OiLPMfFbIaqsn/Mo/T u2hmjDtyqpKZMSxZRrIOSbtV++5t0AO03SQzBc5hWrLWSufLf5zwtvgL+aEgorWGMdq4Y0 TIwyirsdMIgYr87roTZOEDKY2ziU3tq94p3Ddmr5F2XNaYtm+Qauvj72J6UXJLyh/5722X QYjbetF+ckEuZuMDY5VwZbr29FhkAz39Nk2IrkLoTBK1drsw6JDDC7TmlCG6FjqyjWlVT5 knUVrqYAMx7bokgLqoGSVTlF69D6Juvt2O2VWve3FUrnRSauw7Klt4ln3Nbx4w== From: Daniil Gnusarev To: gnusarevda@basealt.ru, devel-kernel@lists.altlinux.org Date: Wed, 11 Feb 2026 12:41:17 +0400 Message-ID: <20260211084122.353558-6-gnusarevda@basealt.ru> X-Mailer: git-send-email 2.42.2 In-Reply-To: <20260211084122.353558-1-gnusarevda@basealt.ru> References: <20260211084122.353558-1-gnusarevda@basealt.ru> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [d-kernel] [PATCH 5/7] arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588 X-BeenThere: devel-kernel@lists.altlinux.org X-Mailman-Version: 2.1.12 Precedence: list Reply-To: ALT Linux kernel packages development List-Id: ALT Linux kernel packages development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Feb 2026 08:41:52 -0000 Archived-At: List-Archive: List-Post: From: Cristian Ciocaltea Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock provider support"), the HDMI PHY PLL can be used as an alternative and more accurate pixel clock source for VOP2 to improve display modes handling on RK3588 SoC. Add the missing #clock-cells property to allow using the clock provider functionality of HDMI1 PHY. Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-3-f4cec5e06fbe@collabora.com Signed-off-by: Heiko Stuebner (cherry picked from commit aadaa27956e3430217d9e6b8af5880e39b05b961) Signed-off-by: Daniil Gnusarev --- arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi index 9bc5287bb6469..97e55990e0524 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -479,6 +479,7 @@ hdptxphy1: phy@fed70000 { reg = <0x0 0xfed70000 0x0 0x2000>; clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; clock-names = "ref", "apb"; + #clock-cells = <0>; #phy-cells = <0>; resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, -- 2.42.2