From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.1 (2015-04-28) on sa.local.altlinux.org X-Spam-Level: X-Spam-Status: No, score=-3.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RP_MATCHES_RCVD autolearn=ham autolearn_force=no version=3.4.1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=basealt.ru; s=dkim; t=1770637828; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LSgckAmyZkpyqgFefrJlMUwlR5eJsg1XTiDxIIUYUb0=; b=ofOMmPV5nGpdj+OrpEKRpoqjQky5B0JoJRiyBTax4FPUz1qrhzyTeW27jkR8zndhHEceKP jW7pqPstnf2W5KE7nJhPZ9PYMdFeCZOSKXTFpGIr2znSefaCNEleTT/Loj7O/YZHYm3FB0 G1iYFarZuGDU9dl/auForX9JnBXm36RD8Kptx3R6HkqvAhCmrioHojlj6mlYM9cmo/zFI3 oX8btcQ/Gc86mPLaUGlktqY9CAumvMP2ojH0vfMxwoiFkalAiFTeSJrryY32nNIbizkhPC u7YsOwjMfOUzck6Uxq8uht+FX3ueBVJyNhNlH4+2srYF+BFwkqrxmc/xQJjCvg== From: Daniil Gnusarev To: gnusarevda@basealt.ru, devel-kernel@lists.altlinux.org Date: Mon, 9 Feb 2026 15:50:08 +0400 Message-ID: <20260209115011.380925-3-gnusarevda@basealt.ru> X-Mailer: git-send-email 2.42.2 In-Reply-To: <20260209115011.380925-1-gnusarevda@basealt.ru> References: <20260209115011.380925-1-gnusarevda@basealt.ru> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [d-kernel] [PATCH 2/3] arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588 X-BeenThere: devel-kernel@lists.altlinux.org X-Mailman-Version: 2.1.12 Precedence: list Reply-To: ALT Linux kernel packages development List-Id: ALT Linux kernel packages development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Feb 2026 11:50:34 -0000 Archived-At: List-Archive: List-Post: From: Cristian Ciocaltea VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and more accurate pixel clock source to improve handling of display modes up to 4K@60Hz on video ports 0, 1 and 2. For now only HDMI0 output is supported, hence add the related PLL clock. Tested-by: FUKAUMI Naoki Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-5-d71c6a196e58@collabora.com Signed-off-by: Heiko Stuebner (cherry picked from commit eb4262203d7d85eb7b6f2696816db272e41f5464) Signed-off-by: Daniil Gnusarev --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index fed1128671b0f..030afd5f64448 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1260,14 +1260,16 @@ vop: vop@fdd90000 { <&cru DCLK_VOP1>, <&cru DCLK_VOP2>, <&cru DCLK_VOP3>, - <&cru PCLK_VOP_ROOT>; + <&cru PCLK_VOP_ROOT>, + <&hdptxphy_hdmi0>; clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2", "dclk_vp3", - "pclk_vop"; + "pclk_vop", + "pll_hdmiphy0"; iommus = <&vop_mmu>; power-domains = <&power RK3588_PD_VOP>; rockchip,grf = <&sys_grf>; -- 2.42.2