From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.1 (2015-04-28) on sa.local.altlinux.org X-Spam-Level: X-Spam-Status: No, score=-3.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RP_MATCHES_RCVD autolearn=ham autolearn_force=no version=3.4.1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=basealt.ru; s=dkim; t=1770637828; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=u1uIsxgolP0ehMkIGb/5efNPG/xQ1xztQV26mYKniak=; b=NzT2t+BJ3gZJxgmQD+7biR17cjMN7UypCIW9duIz+5EdX2P1ROWcM/fnZbyCIpWp8Ygf1h 7ZPg8oOVg6gGYNbdNRyIXevOdQvW2sSZzVlW+mB1Uq3zao2KGrRfUEvy+NhxCSnXcuEb3R iMpAfThMuPjJmVX5AwRSEFOA7m25vdNEN3u4qGFBwy98xL2KuZ0SQmZPN3oezv0ugI02Dk 1daODOk4PzoCg5KNrEHKe/lV/iRN6VJcfAIVcSTV8w0jJwEf3SBTb+rELmE7/S50mbEOWB 6AoJ+QtU+/b7n89A6HlCTKFT1U9F/LXoZnB0UZ45EOf1t7VME41Oq4zQNNYA2A== From: Daniil Gnusarev To: gnusarevda@basealt.ru, devel-kernel@lists.altlinux.org Date: Mon, 9 Feb 2026 15:50:07 +0400 Message-ID: <20260209115011.380925-2-gnusarevda@basealt.ru> X-Mailer: git-send-email 2.42.2 In-Reply-To: <20260209115011.380925-1-gnusarevda@basealt.ru> References: <20260209115011.380925-1-gnusarevda@basealt.ru> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [d-kernel] [PATCH 1/3] arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588 X-BeenThere: devel-kernel@lists.altlinux.org X-Mailman-Version: 2.1.12 Precedence: list Reply-To: ALT Linux kernel packages development List-Id: ALT Linux kernel packages development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Feb 2026 11:50:30 -0000 Archived-At: List-Archive: List-Post: From: Cristian Ciocaltea Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock provider support"), the HDMI PHY PLL can be used as an alternative and more accurate pixel clock source for VOP2 to improve display modes handling on RK3588 SoC. Add the missing #clock-cells property to allow using the clock provider functionality of HDMI0 PHY. Signed-off-by: Cristian Ciocaltea Tested-by: FUKAUMI Naoki Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-4-d71c6a196e58@collabora.com Signed-off-by: Heiko Stuebner (cherry picked from commit d0f17738778c12be629ba77ff00c43c3e9eb8428) Signed-off-by: Daniil Gnusarev --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 3b02d8c5bf4d3..fed1128671b0f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -2811,6 +2811,7 @@ hdptxphy_hdmi0: phy@fed60000 { reg = <0x0 0xfed60000 0x0 0x2000>; clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; clock-names = "ref", "apb"; + #clock-cells = <0>; #phy-cells = <0>; resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, -- 2.42.2