From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.1 (2015-04-28) on sa.local.altlinux.org X-Spam-Level: X-Spam-Status: No, score=-4.3 required=5.0 tests=ALL_TRUSTED,BAYES_00, RP_MATCHES_RCVD autolearn=unavailable autolearn_force=no version=3.4.1 From: Daniil Gnusarev To: devel-kernel@lists.altlinux.org Date: Mon, 14 Oct 2024 18:02:11 +0400 Message-ID: <20241014140221.535985-31-gnusarevda@basealt.ru> X-Mailer: git-send-email 2.42.2 In-Reply-To: <20241014140221.535985-1-gnusarevda@basealt.ru> References: <20241014140221.535985-1-gnusarevda@basealt.ru> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [d-kernel] [PATCH 30/39] pci: baikal-pcie: driver compatibility with SDK earlier than 5.7 X-BeenThere: devel-kernel@lists.altlinux.org X-Mailman-Version: 2.1.12 Precedence: list Reply-To: ALT Linux kernel packages development List-Id: ALT Linux kernel packages development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 14 Oct 2024 14:02:16 -0000 Archived-At: List-Archive: List-Post: In earlier SDKs before version 5.7, there is no "gpr" parameter in devicetree for PCIe devices. Instead, the specified "lrcu" is used with the required offset. Signed-off-by: Daniil Gnusarev --- drivers/pci/controller/dwc/pcie-baikal-core.c | 50 +++++++++++-------- 1 file changed, 30 insertions(+), 20 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-baikal-core.c b/drivers/pci/controller/dwc/pcie-baikal-core.c index 8e23af9950494..19cb589e48db6 100644 --- a/drivers/pci/controller/dwc/pcie-baikal-core.c +++ b/drivers/pci/controller/dwc/pcie-baikal-core.c @@ -121,6 +121,8 @@ static bool baikal_pcie_link_wait_training_done(struct dw_pcie *pci) #define BM1000_PCIE_HOT_RST BIT(12) #define BM1000_PCIE_ADB_PWRDWN BIT(13) +#define BM1000_PCIE_GPR_OFFSET 0x50000 + #define BM1000_PCIE_GPR_STATUS_BASE 0x04 #define BM1000_PCIE_GPR_STATUS(x) (((x) * 0x20) + BM1000_PCIE_GPR_STATUS_BASE) @@ -143,6 +145,7 @@ struct bm1000_pcie { struct dw_pcie *pci; unsigned int num; struct regmap *gpr; + uintptr_t gpr_offset; union { struct gpio_desc *reset_gpio; struct { @@ -160,9 +163,9 @@ void bm1000_pcie_phy_enable(struct dw_pcie *pci) struct bm1000_pcie *bm = dev_get_drvdata(pci->dev); u32 reg; - regmap_read(bm->gpr, BM1000_PCIE_GPR_GENCTL(bm->num), ®); + regmap_read(bm->gpr, bm->gpr_offset + BM1000_PCIE_GPR_GENCTL(bm->num), ®); reg |= BM1000_PCIE_PHY_MGMT_ENABLE | BM1000_PCIE_DBI2_MODE; - regmap_write(bm->gpr, BM1000_PCIE_GPR_GENCTL(bm->num), reg); + regmap_write(bm->gpr, bm->gpr_offset + BM1000_PCIE_GPR_GENCTL(bm->num), reg); } void bm1000_pcie_phy_disable(struct dw_pcie *pci) @@ -170,9 +173,9 @@ void bm1000_pcie_phy_disable(struct dw_pcie *pci) struct bm1000_pcie *bm = dev_get_drvdata(pci->dev); u32 reg; - regmap_read(bm->gpr, BM1000_PCIE_GPR_GENCTL(bm->num), ®); + regmap_read(bm->gpr, bm->gpr_offset + BM1000_PCIE_GPR_GENCTL(bm->num), ®); reg &= ~(BM1000_PCIE_PHY_MGMT_ENABLE | BM1000_PCIE_DBI2_MODE); - regmap_write(bm->gpr, BM1000_PCIE_GPR_GENCTL(bm->num), reg); + regmap_write(bm->gpr, bm->gpr_offset + BM1000_PCIE_GPR_GENCTL(bm->num), reg); } static int bm1000_get_resources(struct platform_device *pdev, @@ -184,10 +187,16 @@ static int bm1000_get_resources(struct platform_device *pdev, struct resource *res; bm->pci = pci; + bm->gpr_offset = 0; bm->gpr = syscon_regmap_lookup_by_compatible("baikal,bm1000-pcie-gpr"); if (IS_ERR(bm->gpr)) { - dev_err(dev, "failed to find PCIe GPR registers\n"); - return PTR_ERR(bm->gpr); + dev_warn(dev, "failed to find PCIe GPR registers, trying LCRU\n"); + bm->gpr = syscon_regmap_lookup_by_phandle(dev->of_node, "baikal,pcie-lcru"); + if (IS_ERR(bm->gpr)) { + dev_err(dev, "failed to find PCIe LCRU registers\n"); + return PTR_ERR(bm->gpr); + } + bm->gpr_offset = BM1000_PCIE_GPR_OFFSET; } res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); @@ -223,11 +232,11 @@ static int bm1000_pcie_link_up(struct dw_pcie *pci) struct bm1000_pcie *bm = dev_get_drvdata(pci->dev); u32 reg; - regmap_read(bm->gpr, BM1000_PCIE_GPR_GENCTL(bm->num), ®); + regmap_read(bm->gpr, bm->gpr_offset + BM1000_PCIE_GPR_GENCTL(bm->num), ®); if (!(reg & BM1000_PCIE_LTSSM_ENABLE)) return 0; - regmap_read(bm->gpr, BM1000_PCIE_GPR_STATUS(bm->num), ®); + regmap_read(bm->gpr, bm->gpr_offset + BM1000_PCIE_GPR_STATUS(bm->num), ®); return (reg & BAIKAL_PCIE_LTSSM_MASK) == BAIKAL_PCIE_LTSSM_STATE_L0; } @@ -236,9 +245,9 @@ static int bm1000_pcie_start_link(struct dw_pcie *pci) struct bm1000_pcie *bm = dev_get_drvdata(pci->dev); u32 reg; - regmap_read(bm->gpr, BM1000_PCIE_GPR_GENCTL(bm->num), ®); + regmap_read(bm->gpr, bm->gpr_offset + BM1000_PCIE_GPR_GENCTL(bm->num), ®); reg |= BM1000_PCIE_LTSSM_ENABLE; - regmap_write(bm->gpr, BM1000_PCIE_GPR_GENCTL(bm->num), reg); + regmap_write(bm->gpr, bm->gpr_offset + BM1000_PCIE_GPR_GENCTL(bm->num), reg); return 0; } @@ -453,9 +462,9 @@ static int bm1000_pcie_host_init(struct dw_pcie_rp *pp) /* If link is not established yet, reset the RC */ if (!linkup) { /* Disable link training */ - regmap_read(bm->gpr, BM1000_PCIE_GPR_GENCTL(bm->num), ®); + regmap_read(bm->gpr, bm->gpr_offset + BM1000_PCIE_GPR_GENCTL(bm->num), ®); reg &= ~BM1000_PCIE_LTSSM_ENABLE; - regmap_write(bm->gpr, BM1000_PCIE_GPR_GENCTL(bm->num), reg); + regmap_write(bm->gpr, bm->gpr_offset + BM1000_PCIE_GPR_GENCTL(bm->num), reg); /* Assert PERST pin */ if (acpi_disabled) { @@ -479,7 +488,7 @@ static int bm1000_pcie_host_init(struct dw_pcie_rp *pp) } /* Reset the RC */ - regmap_read(bm->gpr, BM1000_PCIE_GPR_RESET(bm->num), ®); + regmap_read(bm->gpr, bm->gpr_offset + BM1000_PCIE_GPR_RESET(bm->num), ®); reg |= BM1000_PCIE_NONSTICKY_RST | BM1000_PCIE_STICKY_RST | BM1000_PCIE_PWR_RST | @@ -494,7 +503,7 @@ static int bm1000_pcie_host_init(struct dw_pcie_rp *pp) reg |= BM1000_PCIE_PIPE_RST; } - regmap_write(bm->gpr, BM1000_PCIE_GPR_RESET(bm->num), reg); + regmap_write(bm->gpr, bm->gpr_offset + BM1000_PCIE_GPR_RESET(bm->num), reg); if (!acpi_disabled && bm->num == 2 && bm->gpio[1].is_set) { /* Assert PRSNT pin */ @@ -510,12 +519,12 @@ static int bm1000_pcie_host_init(struct dw_pcie_rp *pp) bm1000_pcie_set_gpio(bm->gpio[0].num, bm->gpio[0].polarity); /* Deassert PHY reset */ - regmap_read(bm->gpr, BM1000_PCIE_GPR_RESET(bm->num), ®); + regmap_read(bm->gpr, bm->gpr_offset + BM1000_PCIE_GPR_RESET(bm->num), ®); reg &= ~BM1000_PCIE_PHY_RST; - regmap_write(bm->gpr, BM1000_PCIE_GPR_RESET(bm->num), reg); + regmap_write(bm->gpr, bm->gpr_offset + BM1000_PCIE_GPR_RESET(bm->num), reg); /* Deassert all software controlled resets */ - regmap_read(bm->gpr, BM1000_PCIE_GPR_RESET(bm->num), ®); + regmap_read(bm->gpr, bm->gpr_offset + BM1000_PCIE_GPR_RESET(bm->num), ®); reg &= ~(BM1000_PCIE_ADB_PWRDWN | BM1000_PCIE_HOT_RST | BM1000_PCIE_NONSTICKY_RST | @@ -531,7 +540,7 @@ static int bm1000_pcie_host_init(struct dw_pcie_rp *pp) reg &= ~BM1000_PCIE_PIPE_RST; } - regmap_write(bm->gpr, BM1000_PCIE_GPR_RESET(bm->num), reg); + regmap_write(bm->gpr, bm->gpr_offset + BM1000_PCIE_GPR_RESET(bm->num), reg); } /* Enable error reporting */ @@ -567,11 +576,11 @@ static int bm1000_pcie_host_init(struct dw_pcie_rp *pp) dw_pcie_writew_dbi(pci, exp_cap_off + PCI_EXP_LNKCTL2, reg); } - regmap_read(bm->gpr, BM1000_PCIE_GPR_MSI_TRANS_CTL2, ®); + regmap_read(bm->gpr, bm->gpr_offset + BM1000_PCIE_GPR_MSI_TRANS_CTL2, ®); reg &= ~BM1000_PCIE_MSI_TRANS_RCNUM_MASK(bm->num); reg |= BM1000_PCIE_MSI_TRANS_RCNUM(bm->num); reg |= BM1000_PCIE_MSI_TRANS_EN(bm->num); - regmap_write(bm->gpr, BM1000_PCIE_GPR_MSI_TRANS_CTL2, reg); + regmap_write(bm->gpr, bm->gpr_offset + BM1000_PCIE_GPR_MSI_TRANS_CTL2, reg); /* RX/TX equalizers fine tune */ bm1000_pcie_tune(pci); @@ -1124,6 +1133,7 @@ static int bm1000_get_acpi_data(struct device *dev, struct bm1000_pcie *bm, struct acpi_device *adev = to_acpi_device(dev), *res_dev; int ret; + bm->gpr_offset = 0; bm->gpr = bm1000_pcie_get_gpr_acpi(bm); if (IS_ERR_OR_NULL(bm->gpr)) { dev_err(dev, "No PCIe GPR specified\n"); -- 2.42.2