From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Wed, 14 Dec 2022 18:06:20 +0300 From: Vitaly Chikunov To: ALT Linux kernel packages development Message-ID: <20221214150620.ainzrgm2ivdleijx@altlinux.org> References: <20221214131919.681481-1-asheplyakov@basealt.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=koi8-r Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20221214131919.681481-1-asheplyakov@basealt.ru> Cc: =?koi8-r?B?8s/Nwc4g89TB18PF1w==?= , =?koi8-r?B?5M3J1NLJyiD0xdKjyMnO?= , =?koi8-r?B?6cfP0tgg/tXEz9c=?= , =?koi8-r?B?5dfHxc7JyiDzyc7FzNjOycvP1w==?= Subject: Re: [d-kernel] [PATCH 01/32] clk: added Baikal-M clock management unit driver X-BeenThere: devel-kernel@lists.altlinux.org X-Mailman-Version: 2.1.12 Precedence: list Reply-To: ALT Linux kernel packages development List-Id: ALT Linux kernel packages development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 14 Dec 2022 15:06:22 -0000 Archived-At: List-Archive: List-Post: Видимо, это для v6.1. Пропущен patch 32/32 и cover letter. Было бы удобнее получать этот patchset в виде pull request. Спасибо. On Wed, Dec 14, 2022 at 05:18:48PM +0400, Alexey Sheplyakov wrote: > On Baikal-M SoC clock management unit (CMU) is controled by > the firmware (ARM-TF), since the registers of CMU are accessible > only to the secure world. This drivers is a shim which calls into > the firmware. > > Signed-off-by: Alexey Sheplyakov > Co-developed-by: Ekaterina Skachko > X-feature-Baikal-M > --- > drivers/clk/Makefile | 1 + > drivers/clk/baikal-m/Makefile | 1 + > drivers/clk/baikal-m/clk-baikal.c | 356 ++++++++++++++++++++++++++++++ > 3 files changed, 358 insertions(+) > create mode 100644 drivers/clk/baikal-m/Makefile > create mode 100644 drivers/clk/baikal-m/clk-baikal.c > > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile > index e3ca0d058a25..37615a5ff451 100644 > --- a/drivers/clk/Makefile > +++ b/drivers/clk/Makefile > @@ -83,6 +83,7 @@ obj-y += analogbits/ > obj-$(CONFIG_COMMON_CLK_AT91) += at91/ > obj-$(CONFIG_ARCH_ARTPEC) += axis/ > obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/ > +obj-$(CONFIG_ARCH_BAIKAL) += baikal-m/ > obj-$(CONFIG_CLK_BAIKAL_T1) += baikal-t1/ > obj-y += bcm/ > obj-$(CONFIG_ARCH_BERLIN) += berlin/ > diff --git a/drivers/clk/baikal-m/Makefile b/drivers/clk/baikal-m/Makefile > new file mode 100644 > index 000000000000..56aa4de4081c > --- /dev/null > +++ b/drivers/clk/baikal-m/Makefile > @@ -0,0 +1 @@ > +obj-y += clk-baikal.o > \ No newline at end of file > diff --git a/drivers/clk/baikal-m/clk-baikal.c b/drivers/clk/baikal-m/clk-baikal.c > new file mode 100644 > index 000000000000..b3adcb727458 > --- /dev/null > +++ b/drivers/clk/baikal-m/clk-baikal.c > @@ -0,0 +1,356 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > +/* > + * clk-baikal.c - Baikal-M clock driver. > + * > + * Copyright (C) 2015,2016,2020,2021 Baikal Electronics JSC > + * Authors: > + * Ekaterina Skachko > + * Alexey Sheplyakov > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define CMU_PLL_SET_RATE 0 > +#define CMU_PLL_GET_RATE 1 > +#define CMU_PLL_ENABLE 2 > +#define CMU_PLL_DISABLE 3 > +#define CMU_PLL_ROUND_RATE 4 > +#define CMU_PLL_IS_ENABLED 5 > +#define CMU_CLK_CH_SET_RATE 6 > +#define CMU_CLK_CH_GET_RATE 7 > +#define CMU_CLK_CH_ENABLE 8 > +#define CMU_CLK_CH_DISABLE 9 > +#define CMU_CLK_CH_ROUND_RATE 10 > +#define CMU_CLK_CH_IS_ENABLED 11 > + > +struct baikal_clk_cmu { > + struct clk_hw hw; > + uint32_t cmu_id; > + unsigned int parent; > + const char *name; > + uint32_t is_clk_ch; > +}; > + > +#define to_baikal_cmu(_hw) container_of(_hw, struct baikal_clk_cmu, hw) > + > +/* Pointer to the place on handling SMC CMU calls in monitor */ > +#define BAIKAL_SMC_LCRU_ID 0x82000000 > + > +static int baikal_clk_enable(struct clk_hw *hw) > +{ > + struct arm_smccc_res res; > + struct baikal_clk_cmu *pclk = to_baikal_cmu(hw); > + uint32_t cmd; > + > + if (pclk->is_clk_ch) { > + cmd = CMU_CLK_CH_ENABLE; > + } else { > + cmd = CMU_PLL_ENABLE; > + } > + > + arm_smccc_smc(BAIKAL_SMC_LCRU_ID, pclk->cmu_id, cmd, 0, > + pclk->parent, 0, 0, 0, &res); > + > + pr_debug("%s(%s, %s@0x%x): %s\n", > + __func__, > + pclk->name, > + pclk->is_clk_ch ? "clkch" : "pll", > + pclk->cmu_id, > + res.a0 ? "error" : "ok"); > + > + return res.a0; > +} > + > +static void baikal_clk_disable(struct clk_hw *hw) > +{ > + struct arm_smccc_res res; > + struct baikal_clk_cmu *pclk = to_baikal_cmu(hw); > + uint32_t cmd; > + > + if (pclk->is_clk_ch) { > + cmd = CMU_CLK_CH_DISABLE; > + } else { > + cmd = CMU_PLL_DISABLE; > + } > + > + arm_smccc_smc(BAIKAL_SMC_LCRU_ID, pclk->cmu_id, cmd, 0, > + pclk->parent, 0, 0, 0, &res); > + > + pr_debug("%s(%s, %s@0x%x): %s\n", > + __func__, > + pclk->name, > + pclk->is_clk_ch ? "clkch" : "pll", > + pclk->cmu_id, > + res.a0 ? "error" : "ok"); > +} > + > +static int baikal_clk_is_enabled(struct clk_hw *hw) > +{ > + struct arm_smccc_res res; > + struct baikal_clk_cmu *pclk = to_baikal_cmu(hw); > + uint32_t cmd; > + > + if (pclk->is_clk_ch) { > + cmd = CMU_CLK_CH_IS_ENABLED; > + } else { > + cmd = CMU_PLL_IS_ENABLED; > + } > + > + arm_smccc_smc(BAIKAL_SMC_LCRU_ID, pclk->cmu_id, cmd, 0, > + pclk->parent, 0, 0, 0, &res); > + > + pr_debug("%s(%s, %s@0x%x): %s\n", > + __func__, > + pclk->name, > + pclk->is_clk_ch ? "clkch" : "pll", > + pclk->cmu_id, > + res.a0 ? "true" : "false"); > + > + return res.a0; > +} > + > +static unsigned long baikal_clk_recalc_rate(struct clk_hw *hw, > + unsigned long parent_rate) > +{ > + struct arm_smccc_res res; > + struct baikal_clk_cmu *pclk = to_baikal_cmu(hw); > + uint32_t cmd; > + unsigned long parent; > + > + if (pclk->is_clk_ch) { > + cmd = CMU_CLK_CH_GET_RATE; > + parent = pclk->parent; > + } else { > + cmd = CMU_PLL_GET_RATE; > + parent= parent_rate; > + } > + > + arm_smccc_smc(BAIKAL_SMC_LCRU_ID, pclk->cmu_id, cmd, 0, > + parent, 0, 0, 0, &res); > + > + pr_debug("%s(%s, %s@0x%x): %ld Hz\n", > + __func__, > + pclk->name, > + pclk->is_clk_ch ? "clkch" : "pll", > + pclk->cmu_id, > + res.a0); > + > + return res.a0; > +} > + > +static int baikal_clk_set_rate(struct clk_hw *hw, unsigned long rate, > + unsigned long parent_rate) > +{ > + struct arm_smccc_res res; > + struct baikal_clk_cmu *pclk = to_baikal_cmu(hw); > + uint32_t cmd; > + unsigned long parent; > + > + if (pclk->is_clk_ch) { > + cmd = CMU_CLK_CH_SET_RATE; > + parent = pclk->parent; > + } else { > + cmd = CMU_PLL_SET_RATE; > + parent = parent_rate; > + } > + > + arm_smccc_smc(BAIKAL_SMC_LCRU_ID, pclk->cmu_id, cmd, rate, > + parent, 0, 0, 0, &res); > + > + pr_debug("%s(%s, %s@0x%x, %ld Hz): %s\n", > + __func__, > + pclk->name, > + pclk->is_clk_ch ? "clkch" : "pll", > + pclk->cmu_id, > + rate, > + res.a0 ? "error" : "ok"); > + > + return res.a0; > +} > + > +static long baikal_clk_round_rate(struct clk_hw *hw, unsigned long rate, > + unsigned long *prate) > +{ > + struct arm_smccc_res res; > + struct baikal_clk_cmu *pclk = to_baikal_cmu(hw); > + unsigned long parent; > + uint32_t cmd; > + > + if (pclk->is_clk_ch) { > + cmd = CMU_CLK_CH_ROUND_RATE; > + parent = pclk->parent; > + } else { > + cmd = CMU_PLL_ROUND_RATE; > + parent = *prate; > + } > + > + arm_smccc_smc(BAIKAL_SMC_LCRU_ID, pclk->cmu_id, cmd, rate, > + parent, 0, 0, 0, &res); > + > + pr_debug("%s(%s, %s@0x%x): %ld Hz\n", > + __func__, > + pclk->name, > + pclk->is_clk_ch ? "clkch" : "pll", > + pclk->cmu_id, > + res.a0); > + > + return res.a0; > +} > + > +static const struct clk_ops be_clk_pll_ops = { > + .enable = baikal_clk_enable, > + .disable = baikal_clk_disable, > + .is_enabled = baikal_clk_is_enabled, > + .recalc_rate = baikal_clk_recalc_rate, > + .set_rate = baikal_clk_set_rate, > + .round_rate = baikal_clk_round_rate > +}; > + > +static int __init baikal_clk_probe(struct device_node *node) > +{ > + struct clk_init_data init; > + struct clk_init_data *init_ch; > + struct baikal_clk_cmu *cmu; > + struct baikal_clk_cmu **cmu_ch; > + > + struct clk *clk; > + struct clk_onecell_data *clk_ch; > + > + int number, i = 0; > + u32 rc, index; > + struct property *prop; > + const __be32 *p; > + const char *clk_ch_name; > + const char *parent_name; > + > + cmu = kzalloc(sizeof(struct baikal_clk_cmu), GFP_KERNEL); > + if (!cmu) { > + pr_err("%s: could not allocate CMU clk\n", __func__); > + return -ENOMEM; > + } > + > + of_property_read_string(node, "clock-output-names", &cmu->name); > + of_property_read_u32(node, "clock-frequency", &cmu->parent); > + of_property_read_u32(node, "cmu-id", &cmu->cmu_id); > + > + parent_name = of_clk_get_parent_name(node, 0); > + > + /* Setup clock init structure */ > + init.parent_names = &parent_name; > + init.num_parents = 1; > + init.name = cmu->name; > + init.ops = &be_clk_pll_ops; > + init.flags = CLK_IGNORE_UNUSED; > + > + cmu->hw.init = &init; > + cmu->is_clk_ch = 0; > + > + /* Register the clock */ > + pr_debug("%s: add %s, parent %s\n", __func__, cmu->name, parent_name ? parent_name : "null"); > + clk = clk_register(NULL, &cmu->hw); > + > + if (IS_ERR(clk)) { > + pr_err("%s: could not register clk %s\n", __func__, cmu->name); > + return -ENOMEM; > + } > + > + /* Register the clock for lookup */ > + rc = clk_register_clkdev(clk, cmu->name, NULL); > + if (rc != 0) { > + pr_err("%s: could not register lookup clk %s\n", > + __func__, cmu->name); > + } > + > + clk_prepare_enable(clk); > + > + number = of_property_count_u32_elems(node, "clock-indices"); > + > + if (number > 0) { > + clk_ch = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); > + if (!clk_ch) { > + pr_err("%s: could not allocate CMU clk channel\n", __func__); > + return -ENOMEM; > + } > + > + /* Get the last index to find out max number of children*/ > + of_property_for_each_u32(node, "clock-indices", prop, p, index) { > + ; > + } > + > + clk_ch->clks = kcalloc(index + 1, sizeof(struct clk *), GFP_KERNEL); > + clk_ch->clk_num = index + 1; > + cmu_ch = kcalloc((index + 1), sizeof(struct baikal_clk_cmu *), GFP_KERNEL); > + if (!cmu_ch) { > + kfree(clk_ch); > + return -ENOMEM; > + } > + init_ch = kcalloc((number + 1), sizeof(struct clk_init_data), GFP_KERNEL); > + if (!init_ch) { > + pr_err("%s: could not allocate CMU init structure \n", __func__); > + kfree(cmu_ch); > + kfree(clk_ch); > + return -ENOMEM; > + } > + > + of_property_for_each_u32(node, "clock-indices", prop, p, index) { > + of_property_read_string_index(node, "clock-names", > + i, &clk_ch_name); > + pr_info("%s: clkch <%s>, index %d, i %d\n", __func__, clk_ch_name, index, i); > + init_ch[i].parent_names = &cmu->name; > + init_ch[i].num_parents = 1; > + init_ch[i].name = clk_ch_name; > + init_ch[i].ops = &be_clk_pll_ops; > + init_ch[i].flags = CLK_IGNORE_UNUSED; > + > + cmu_ch[index] = kzalloc(sizeof(struct baikal_clk_cmu), GFP_KERNEL); > + if (!cmu_ch[index]) { > + pr_err("%s: could not allocate baikal_clk_cmu structure\n", __func__); > + return -ENOMEM; > + } > + cmu_ch[index]->name = clk_ch_name; > + cmu_ch[index]->cmu_id = index; > + cmu_ch[index]->parent = cmu->cmu_id; > + cmu_ch[index]->is_clk_ch = 1; > + cmu_ch[index]->hw.init = &init_ch[i]; > + clk_ch->clks[index] = clk_register(NULL, &cmu_ch[index]->hw); > + > + if (IS_ERR(clk_ch->clks[index])) { > + pr_err("%s: could not register clk %s\n", __func__, clk_ch_name); > + } > + > + rc = clk_register_clkdev(clk_ch->clks[index], clk_ch_name, NULL); > + if (rc != 0) { > + pr_err("%s: could not register lookup clk %s\n", > + __func__, clk_ch_name); > + } > + > + clk_prepare_enable(clk_ch->clks[index]); > + i++; > + } > + > + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_ch); > + } > + > + return of_clk_add_provider(node, of_clk_src_simple_get, clk); > +} > + > +static void __init baikal_clk_init(struct device_node *np) > +{ > + int err; > + err = baikal_clk_probe(np); > + if (err) { > + panic("%s: failed to probe clock %pOF: %d\n", __func__, np, err); > + } else { > + pr_info("%s: successfully probed %pOF\n", __func__, np); > + } > +} > +CLK_OF_DECLARE_DRIVER(baikal_cmu, "baikal,cmu", baikal_clk_init); > +CLK_OF_DECLARE_DRIVER(bm1000_cmu, "baikal,bm1000-cmu", baikal_clk_init); > -- > 2.33.5 > > _______________________________________________ > devel-kernel mailing list > devel-kernel@lists.altlinux.org > https://lists.altlinux.org/mailman/listinfo/devel-kernel