From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.1 (2015-04-28) on sa.local.altlinux.org X-Spam-Level: X-Spam-Status: No, score=-4.3 required=5.0 tests=ALL_TRUSTED,BAYES_00, RP_MATCHES_RCVD autolearn=unavailable autolearn_force=no version=3.4.1 From: Alexey Sheplyakov To: devel-kernel@lists.altlinux.org Date: Wed, 14 Dec 2022 17:19:08 +0400 Message-Id: <20221214131919.681481-21-asheplyakov@basealt.ru> X-Mailer: git-send-email 2.33.5 In-Reply-To: <20221214131919.681481-1-asheplyakov@basealt.ru> References: <20221214131919.681481-1-asheplyakov@basealt.ru> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Cc: =?UTF-8?q?=D0=A0=D0=BE=D0=BC=D0=B0=D0=BD=20=D0=A1=D1=82=D0=B0=D0=B2=D1=86=D0=B5=D0=B2?= , =?UTF-8?q?=D0=98=D0=B3=D0=BE=D1=80=D1=8C=20=D0=A7=D1=83=D0=B4=D0=BE=D0=B2?= , =?UTF-8?q?=D0=95=D0=B2=D0=B3=D0=B5=D0=BD=D0=B8=D0=B9=20=D0=A1=D0=B8=D0=BD=D0=B5=D0=BB=D1=8C=D0=BD=D0=B8=D0=BA=D0=BE=D0=B2?= , =?UTF-8?q?=D0=94=D0=BC=D0=B8=D1=82=D1=80=D0=B8=D0=B9=20=D0=A2=D0=B5=D1=80=D1=91=D1=85=D0=B8=D0=BD?= Subject: [d-kernel] [PATCH 21/32] drm/bridge: dw-hdmi: support ahb audio hw revision 0x2a X-BeenThere: devel-kernel@lists.altlinux.org X-Mailman-Version: 2.1.12 Precedence: list Reply-To: ALT Linux kernel packages development List-Id: ALT Linux kernel packages development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 14 Dec 2022 13:20:23 -0000 Archived-At: List-Archive: List-Post: The hardware needs non-zero register shift (from DTB), and a special conf0 parameter. With this patch I can use HDMI audio on Baikal-M SoC. Signed-off-by: Alexey Sheplyakov X-feature-Baikal-M --- .../drm/bridge/synopsys/dw-hdmi-ahb-audio.c | 106 ++++++++++++------ .../gpu/drm/bridge/synopsys/dw-hdmi-audio.h | 1 + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 5 + 3 files changed, 77 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c index 4efb62bcdb63..ec32b531dfd4 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c @@ -132,12 +132,45 @@ struct snd_dw_hdmi { u8 cs[192][8]; }; -static void dw_hdmi_writel(u32 val, void __iomem *ptr) +static inline void dw_hdmi_writeb_relaxed(u8 value, const struct dw_hdmi_audio_data *data, int offset) { - writeb_relaxed(val, ptr); - writeb_relaxed(val >> 8, ptr + 1); - writeb_relaxed(val >> 16, ptr + 2); - writeb_relaxed(val >> 24, ptr + 3); + void __iomem *base = data->base; + if (data->regshift != 0) + offset <<= data->regshift; + writeb_relaxed(value, base + offset); +} + +static inline void dw_hdmi_writeb(u8 value, const struct dw_hdmi_audio_data *data, int offset) +{ + void __iomem *base = data->base; + if (data->regshift != 0) + offset <<= data->regshift; + writeb(value, base + offset); +} + +static inline u8 dw_hdmi_readb(const struct dw_hdmi_audio_data *data, int offset) +{ + void __iomem *base = data->base; + if (data->regshift != 0) + offset <<= data->regshift; + return readb(base + offset); + +} + +static inline u8 dw_hdmi_readb_relaxed(const struct dw_hdmi_audio_data *data, int offset) +{ + void __iomem *base = data->base; + if (data->regshift != 0) + offset <<= data->regshift; + return readb_relaxed(base + offset); +} + +static void dw_hdmi_writel(u32 val, const struct dw_hdmi_audio_data *data, int offset) +{ + dw_hdmi_writeb_relaxed(val, data, offset); + dw_hdmi_writeb_relaxed(val >> 8, data, offset + 1); + dw_hdmi_writeb_relaxed(val >> 16, data, offset + 2); + dw_hdmi_writeb_relaxed(val >> 24, data, offset + 3); } /* @@ -232,7 +265,6 @@ static void dw_hdmi_create_cs(struct snd_dw_hdmi *dw, static void dw_hdmi_start_dma(struct snd_dw_hdmi *dw) { - void __iomem *base = dw->data.base; unsigned offset = dw->buf_offset; unsigned period = dw->buf_period; u32 start, stop; @@ -240,18 +272,18 @@ static void dw_hdmi_start_dma(struct snd_dw_hdmi *dw) dw->reformat(dw, offset, period); /* Clear all irqs before enabling irqs and starting DMA */ - writeb_relaxed(HDMI_IH_AHBDMAAUD_STAT0_ALL, - base + HDMI_IH_AHBDMAAUD_STAT0); + dw_hdmi_writeb_relaxed(HDMI_IH_AHBDMAAUD_STAT0_ALL, + &dw->data, HDMI_IH_AHBDMAAUD_STAT0); start = dw->buf_addr + offset; stop = start + period - 1; /* Setup the hardware start/stop addresses */ - dw_hdmi_writel(start, base + HDMI_AHB_DMA_STRADDR0); - dw_hdmi_writel(stop, base + HDMI_AHB_DMA_STPADDR0); + dw_hdmi_writel(start, &dw->data, HDMI_AHB_DMA_STRADDR0); + dw_hdmi_writel(stop, &dw->data, HDMI_AHB_DMA_STPADDR0); - writeb_relaxed((u8)~HDMI_AHB_DMA_MASK_DONE, base + HDMI_AHB_DMA_MASK); - writeb(HDMI_AHB_DMA_START_START, base + HDMI_AHB_DMA_START); + dw_hdmi_writeb_relaxed((u8)~HDMI_AHB_DMA_MASK_DONE, &dw->data, HDMI_AHB_DMA_MASK); + dw_hdmi_writeb(HDMI_AHB_DMA_START_START, &dw->data, HDMI_AHB_DMA_START); offset += period; if (offset >= dw->buf_size) @@ -262,8 +294,8 @@ static void dw_hdmi_start_dma(struct snd_dw_hdmi *dw) static void dw_hdmi_stop_dma(struct snd_dw_hdmi *dw) { /* Disable interrupts before disabling DMA */ - writeb_relaxed(~0, dw->data.base + HDMI_AHB_DMA_MASK); - writeb_relaxed(HDMI_AHB_DMA_STOP_STOP, dw->data.base + HDMI_AHB_DMA_STOP); + dw_hdmi_writeb_relaxed(~0, &dw->data, HDMI_AHB_DMA_MASK); + dw_hdmi_writeb_relaxed(HDMI_AHB_DMA_STOP_STOP, &dw->data, HDMI_AHB_DMA_STOP); } static irqreturn_t snd_dw_hdmi_irq(int irq, void *data) @@ -272,11 +304,11 @@ static irqreturn_t snd_dw_hdmi_irq(int irq, void *data) struct snd_pcm_substream *substream; unsigned stat; - stat = readb_relaxed(dw->data.base + HDMI_IH_AHBDMAAUD_STAT0); + stat = dw_hdmi_readb_relaxed(&dw->data, HDMI_IH_AHBDMAAUD_STAT0); if (!stat) return IRQ_NONE; - writeb_relaxed(stat, dw->data.base + HDMI_IH_AHBDMAAUD_STAT0); + dw_hdmi_writeb_relaxed(stat, &dw->data, HDMI_IH_AHBDMAAUD_STAT0); substream = dw->substream; if (stat & HDMI_IH_AHBDMAAUD_STAT0_DONE && substream) { @@ -319,7 +351,6 @@ static int dw_hdmi_open(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct snd_dw_hdmi *dw = substream->private_data; - void __iomem *base = dw->data.base; u8 *eld; int ret; @@ -349,16 +380,16 @@ static int dw_hdmi_open(struct snd_pcm_substream *substream) return ret; /* Clear FIFO */ - writeb_relaxed(HDMI_AHB_DMA_CONF0_SW_FIFO_RST, - base + HDMI_AHB_DMA_CONF0); + dw_hdmi_writeb_relaxed(HDMI_AHB_DMA_CONF0_SW_FIFO_RST, + &dw->data, HDMI_AHB_DMA_CONF0); /* Configure interrupt polarities */ - writeb_relaxed(~0, base + HDMI_AHB_DMA_POL); - writeb_relaxed(~0, base + HDMI_AHB_DMA_BUFFPOL); + dw_hdmi_writeb_relaxed(~0, &dw->data, HDMI_AHB_DMA_POL); + dw_hdmi_writeb_relaxed(~0, &dw->data, HDMI_AHB_DMA_BUFFPOL); /* Keep interrupts masked, and clear any pending */ - writeb_relaxed(~0, base + HDMI_AHB_DMA_MASK); - writeb_relaxed(~0, base + HDMI_IH_AHBDMAAUD_STAT0); + dw_hdmi_writeb_relaxed(~0, &dw->data, HDMI_AHB_DMA_MASK); + dw_hdmi_writeb_relaxed(~0, &dw->data, HDMI_IH_AHBDMAAUD_STAT0); ret = request_irq(dw->data.irq, snd_dw_hdmi_irq, IRQF_SHARED, "dw-hdmi-audio", dw); @@ -366,9 +397,9 @@ static int dw_hdmi_open(struct snd_pcm_substream *substream) return ret; /* Un-mute done interrupt */ - writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL & - ~HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE, - base + HDMI_IH_MUTE_AHBDMAAUD_STAT0); + dw_hdmi_writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL & + ~HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE, + &dw->data, HDMI_IH_MUTE_AHBDMAAUD_STAT0); return 0; } @@ -378,8 +409,8 @@ static int dw_hdmi_close(struct snd_pcm_substream *substream) struct snd_dw_hdmi *dw = substream->private_data; /* Mute all interrupts */ - writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL, - dw->data.base + HDMI_IH_MUTE_AHBDMAAUD_STAT0); + dw_hdmi_writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL, + &dw->data, HDMI_IH_MUTE_AHBDMAAUD_STAT0); free_irq(dw->data.irq, dw); @@ -420,6 +451,11 @@ static int dw_hdmi_prepare(struct snd_pcm_substream *substream) HDMI_AHB_DMA_CONF0_INCR8; threshold = 128; break; + case 0x2a: + conf0 = HDMI_AHB_DMA_CONF0_BURST_MODE | + HDMI_AHB_DMA_CONF0_INCR16; + threshold = 128; + break; default: /* NOTREACHED */ return -EINVAL; @@ -434,9 +470,9 @@ static int dw_hdmi_prepare(struct snd_pcm_substream *substream) conf1 = default_hdmi_channel_config[runtime->channels - 2].conf1; ca = default_hdmi_channel_config[runtime->channels - 2].ca; - writeb_relaxed(threshold, dw->data.base + HDMI_AHB_DMA_THRSLD); - writeb_relaxed(conf0, dw->data.base + HDMI_AHB_DMA_CONF0); - writeb_relaxed(conf1, dw->data.base + HDMI_AHB_DMA_CONF1); + dw_hdmi_writeb_relaxed(threshold, &dw->data, HDMI_AHB_DMA_THRSLD); + dw_hdmi_writeb_relaxed(conf0, &dw->data, HDMI_AHB_DMA_CONF0); + dw_hdmi_writeb_relaxed(conf1, &dw->data, HDMI_AHB_DMA_CONF1); dw_hdmi_set_channel_count(dw->data.hdmi, runtime->channels); dw_hdmi_set_channel_allocation(dw->data.hdmi, ca); @@ -528,10 +564,10 @@ static int snd_dw_hdmi_probe(struct platform_device *pdev) unsigned revision; int ret; - writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL, - data->base + HDMI_IH_MUTE_AHBDMAAUD_STAT0); - revision = readb_relaxed(data->base + HDMI_REVISION_ID); - if (revision != 0x0a && revision != 0x1a) { + dw_hdmi_writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL, + data, HDMI_IH_MUTE_AHBDMAAUD_STAT0); + revision = dw_hdmi_readb_relaxed(data, HDMI_REVISION_ID); + if (revision != 0x0a && revision != 0x1a && revision != 0x2a) { dev_err(dev, "dw-hdmi-audio: unknown revision 0x%02x\n", revision); return -ENXIO; diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h index f72d27208ebe..3250588d39ff 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h @@ -10,6 +10,7 @@ struct dw_hdmi_audio_data { int irq; struct dw_hdmi *hdmi; u8 *(*get_eld)(struct dw_hdmi *hdmi); + unsigned regshift; }; struct dw_hdmi_i2s_audio_data { diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index aa51c61a78c7..49612efe0f1d 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -3572,6 +3572,11 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, audio.irq = irq; audio.hdmi = hdmi; audio.get_eld = hdmi_audio_get_eld; + if (of_property_read_u32(np, "ahb-audio-regshift", &audio.regshift) != 0) { + audio.regshift = 0; + } else { + dev_dbg(dev, "set audio.regshift=%u from DTB\n", audio.regshift); + } hdmi->enable_audio = dw_hdmi_ahb_audio_enable; hdmi->disable_audio = dw_hdmi_ahb_audio_disable; -- 2.33.5