* [d-kernel] [PATCH vtry2 1/7] arm64: dts: wiped out obsolete Baikal-M device trees
2022-09-02 7:33 [d-kernel] (try2) sisyphus/std-def: Байкал-М: поддержка SDK-M 5.5, ноутбука Элпитех Alexey Sheplyakov
@ 2022-09-02 7:33 ` Alexey Sheplyakov
2022-09-02 7:33 ` [d-kernel] [PATCH vtry2 2/7] net: stmmac: removed obsolete Baikal-M specific mdio reset Alexey Sheplyakov
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Alexey Sheplyakov @ 2022-09-02 7:33 UTC (permalink / raw)
To: devel-kernel; +Cc: rst, nir, sin
On Baikal-M Linux receives device tree from firmware (UEFI).
Signed-off-by: Alexey Sheplyakov <asheplyakov@basealt.ru>
---
arch/arm64/boot/dts/Makefile | 1 -
arch/arm64/boot/dts/baikal/Makefile | 9 -
arch/arm64/boot/dts/baikal/bm-dbm.dts | 367 ------
arch/arm64/boot/dts/baikal/bm-mbm.dtsi | 240 ----
arch/arm64/boot/dts/baikal/bm-mbm10.dts | 30 -
arch/arm64/boot/dts/baikal/bm-mbm20.dts | 102 --
arch/arm64/boot/dts/baikal/bm-qemu.dts | 163 ---
arch/arm64/boot/dts/baikal/bm1000-clocks.dtsi | 363 ------
.../arm64/boot/dts/baikal/bm1000-cpufreq.dtsi | 249 ----
arch/arm64/boot/dts/baikal/bm1000.dtsi | 1060 -----------------
10 files changed, 2584 deletions(-)
delete mode 100644 arch/arm64/boot/dts/baikal/Makefile
delete mode 100644 arch/arm64/boot/dts/baikal/bm-dbm.dts
delete mode 100644 arch/arm64/boot/dts/baikal/bm-mbm.dtsi
delete mode 100644 arch/arm64/boot/dts/baikal/bm-mbm10.dts
delete mode 100644 arch/arm64/boot/dts/baikal/bm-mbm20.dts
delete mode 100644 arch/arm64/boot/dts/baikal/bm-qemu.dts
delete mode 100644 arch/arm64/boot/dts/baikal/bm1000-clocks.dtsi
delete mode 100644 arch/arm64/boot/dts/baikal/bm1000-cpufreq.dtsi
delete mode 100644 arch/arm64/boot/dts/baikal/bm1000.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 2cec7300fef2..639e01a4d855 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -8,7 +8,6 @@ subdir-y += amlogic
subdir-y += apm
subdir-y += apple
subdir-y += arm
-subdir-y += baikal
subdir-y += bitmain
subdir-y += broadcom
subdir-y += cavium
diff --git a/arch/arm64/boot/dts/baikal/Makefile b/arch/arm64/boot/dts/baikal/Makefile
deleted file mode 100644
index 9729c6e3d4f3..000000000000
--- a/arch/arm64/boot/dts/baikal/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_ARCH_BAIKAL) += bm-dbm.dtb
-dtb-$(CONFIG_ARCH_BAIKAL) += bm-mbm10.dtb
-dtb-$(CONFIG_ARCH_BAIKAL) += bm-mbm20.dtb
-dtb-$(CONFIG_ARCH_BAIKAL) += bm-qemu.dtb
-
-always := $(dtb-y)
-subdir-y := $(dts-dirs)
-clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/baikal/bm-dbm.dts b/arch/arm64/boot/dts/baikal/bm-dbm.dts
deleted file mode 100644
index 5a180bfda8be..000000000000
--- a/arch/arm64/boot/dts/baikal/bm-dbm.dts
+++ /dev/null
@@ -1,367 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device tree source for Baikal Electronics DBM board
- * Copyright (C) 2019-2021 Baikal Electronics, JSC
- */
-
-/dts-v1/;
-
-#include <dt-bindings/input/input.h>
-#include "bm1000.dtsi"
-
-/ {
- model = "Baikal Electronics DBM";
- compatible = "baikal,baikal-m";
- #address-cells = <2>;
- #size-cells = <2>;
-
- chosen { };
-
- panel {
- compatible = "panel-lvds";
- width-mm = <223>;
- height-mm = <125>;
- data-mapping = "vesa-24";
- panel-timing {
- /* 1920x1080 @ 60 Hz */
- clock-frequency = <148500000>;
- hactive = <1920>;
- vactive = <1080>;
- hsync-len = <44>;
- hfront-porch = <88>;
- hback-porch = <148>;
- vsync-len = <5>;
- vfront-porch = <4>;
- vback-porch = <36>;
- };
- port {
- panel0_lvds0: endpoint@0 {
- remote-endpoint = <&vdu_lvds0_pads>;
- };
- panel0_lvds1: endpoint@1 {
- remote-endpoint = <&vdu_lvds1_pads>;
- };
- };
- };
-
- buttons-backlight {
- compatible = "gpio-keys";
- autorepeat;
- button-brightness-down {
- label = "Brightness Down Button";
- linux,code = <KEY_BRIGHTNESSDOWN>;
- gpios = <&porta 18 GPIO_ACTIVE_LOW>;
- debounce-interval = <50>;
- };
- button-brightness-up {
- label = "Brightness Up Button";
- linux,code = <KEY_BRIGHTNESSUP>;
- gpios = <&porta 17 GPIO_ACTIVE_LOW>;
- debounce-interval = <50>;
- };
- button-brightness-toggle {
- label = "Brightness Toggle Button";
- linux,code = <KEY_BRIGHTNESS_TOGGLE>;
- gpios = <&porta 31 GPIO_ACTIVE_LOW>;
- debounce-interval = <50>;
- };
- };
-
- sound {
- compatible = "baikal,snd_soc_be";
- baikal,cpu-dai = <&i2s>;
- baikal,audio-codec = <&tlv320aic3x>;
- };
-};
-
-&ddr2 {
- status = "okay";
-};
-
-&espi0 {
- cs-gpios = <&porta 28 1>; /* todo: get real gpio */
- status = "okay";
-
- /* test device #0 */
- espi_test0 {
- compatible = "rohm,dh2228fv"; /* same as spidev */
- reg = <0>;
- spi-max-frequency = <12000000>;
- status = "okay";
- };
-};
-
-&gmac0 {
- status = "okay";
- snps,reset-gp-out;
- snps,reset-active-low;
-};
-
-&gmac1 {
- status = "okay";
- snps,reset-gp-out;
- snps,reset-active-low;
-};
-
-&gpio {
- status = "okay";
-};
-
-&gpu {
- system-coherency = <0>;
-};
-
-&hda {
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- tlv320aic3x: tlv320aic3x@18 {
- #sound-dai-cells = <0>;
- compatible = "ti,tlv320aic3x";
- reg = <0x18>;
- reset-gpios = <&porta 4 GPIO_ACTIVE_LOW>;
- status = "okay";
- ai3x-micbias-vg = <1>;
- ai3x-ocmv = <1>;
- };
-
- rtc@56 {
- compatible = "abracon,abeoz9";
- reg = <0x56>;
- };
-};
-
-&i2c1 {
- status = "okay";
-};
-
-&i2s {
- status = "okay";
- sound-dai = <&tlv320aic3x>;
- system-clock-frequency = <12000000>;
-};
-
-&mmc0 {
- status = "okay";
-#if 0
- /* emmc */
- non-removable;
- bus-width = <8>;
- max-clock = <200000000>;
-#else
- /* sd */
- disable-wp;
- bus-width = <4>;
- max-clock = <25000000>;
-#endif
-};
-
-&pcie0 {
- status = "okay";
-};
-
-&pcie1 {
- status = "okay";
-};
-
-&pcie2 {
- status = "okay";
-};
-
-&pcie_lcru {
- status = "okay";
-};
-
-&pvt0 {
- status = "okay";
-};
-
-&pvt1 {
- status = "okay";
-};
-
-&pvt2 {
- status = "okay";
-};
-
-&pvt3 {
- status = "okay";
-};
-
-&pvt_mali {
- status = "okay";
-};
-
-&sata0 {
- status = "okay";
-};
-
-&sata1 {
- status = "okay";
-};
-
-&smbus0 {
- status = "okay";
-};
-
-&smbus1 {
- status = "okay";
-};
-
-&spi0 {
- num-cs = <4>;
- cs-gpios =
- <&porta 24 1>, /* ss0 xp8 - DD53 normal flash */
- <&porta 25 1>, /* ss1 xp9 */
- <&porta 26 1>, /* ss2 xp10 */
- <&porta 27 1>; /* ss3 xp11 */
- status = "okay";
-
- /* SPI flash chip #1 */
- flash0: m25p80@0 {
- compatible = "micron,n25q256a", "jedec,spi-nor";
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <12500000>;
- status = "okay";
-
- /* Flash chip0 partitions */
- mtd0@0 {
- label = "bl1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- mtd1@40000 {
- label = "fip";
- reg = <0x00040000 0x007c0000>;
- };
-
- mtd2@800000 {
- label = "rescue";
- reg = <0x00800000 0x01800000>;
- };
- };
-};
-
-#if 0
-/* undefined */
-&spi1 {
- num-cs = <4>;
- cs-gpios =
- <&porta 20 1>, /* ss0 xp15 - DD57 boot flash */
- <&porta 21 1>, /* ss1 xp16 */
- <&porta 22 1>, /* ss2 xp17 */
- <&porta 23 1>; /* ss3 xp18 */
- status = "okay";
-
- /* SPI flash chip #2 */
- flash0: m25p80@0 {
- compatible = "micron,n25q256a", "jedec,spi-nor";
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <12500000>;
- status = "okay";
-
- /* Flash chip1 partitions */
- mtd0@0 {
- label = "fip_backup";
- reg = <0x00000000 0x00400000>;
- read-only;
- };
-
- mtd1@400000 {
- label = "env_backup";
- reg = <0x00400000 0x00100000>;
- read-only;
- };
-
- mtd2@500000 {
- label = "data1";
- reg = <0x00500000 0x01b00000>;
- };
- };
-};
-#endif
-
-&timer1 {
- status = "okay";
-};
-
-&timer2 {
- status = "okay";
-};
-
-&timer3 {
- status = "okay";
-};
-
-&timer4 {
- status = "okay";
-};
-
-&uart0 {
- status = "okay";
-};
-
-&uart1 {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&vdec {
- status = "okay";
-};
-
-&vdu0 {
- status = "okay";
- enable-gpios = <&porta 16 GPIO_ACTIVE_LOW>;
- backlight {
- min-brightness-level = <10>;
- default-brightness-level = <60>;
- brightness-level-step = <2>;
- pwm-frequency = <20000>;
- };
- port {
- vdu_lvds0_pads: endpoint@0 {
- remote-endpoint = <&panel0_lvds0>;
- };
- vdu_lvds1_pads: endpoint@1 {
- remote-endpoint = <&panel0_lvds1>;
- };
- /*vdu_lvds2_pads: endpoint@2 {
- remote-endpoint = <&panel0_lvds2>;
- };
- vdu_lvds3_pads: endpoint@3 {
- remote-endpoint = <&panel0_lvds3>;
- };*/
- };
-};
-
-&vdu1 {
- status = "okay";
-};
-
-&xgmac0 {
- status = "okay";
-};
-
-&xgmac1 {
- status = "okay";
-};
diff --git a/arch/arm64/boot/dts/baikal/bm-mbm.dtsi b/arch/arm64/boot/dts/baikal/bm-mbm.dtsi
deleted file mode 100644
index 3603db2a465b..000000000000
--- a/arch/arm64/boot/dts/baikal/bm-mbm.dtsi
+++ /dev/null
@@ -1,240 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device tree include file for MBM-compatible boards
- * Copyright (C) 2021 Baikal Electronics, JSC
- */
-
-#include "bm1000.dtsi"
-
-/ {
- model = "Baikal Electronics MBM";
- compatible = "baikal,baikal-m";
- #address-cells = <2>;
- #size-cells = <2>;
-
- chosen { };
-
- leds {
- compatible = "gpio-leds";
- led0 {
- gpios = <&porta 8 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
- };
-
- sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "MITX-Sound-Card";
- simple-audio-card,bitclock-master = <&codec0>;
- simple-audio-card,frame-master = <&codec0>;
- simple-audio-card,widgets =
- "Microphone", "Mic Jack",
- "Headphone", "Headphones",
- "Speaker", "AUX Out",
- "Line", "Line In";
- simple-audio-card,routing =
- "Headphones", "RHP",
- "Headphones", "LHP",
- "AUX Out", "AUXOUT1",
- "AUX Out", "AUXOUT2",
- "L2", "Mic Jack",
- "R2", "Mic Jack",
- "LAUX", "Line In",
- "RAUX", "Line In";
- simple-audio-card,mic-det-gpio = <&porta 26 GPIO_ACTIVE_LOW>;
- simple-audio-card,format = "i2s";
- simple-audio-card,cpu {
- sound-dai = <&i2s>;
- };
- codec0: simple-audio-card,codec {
- sound-dai = <&nau8822 0>;
- };
- };
-};
-
-&ddr2 {
- status = "okay";
-};
-
-&gpio {
- status = "okay";
-};
-
-&gpu {
- system-coherency = <0>;
-};
-
-&hdmi {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- bmc@8 {
- compatible = "tp,mitx2-bmc", "t-platforms,mitx2-bmc";
- reg = <0x08>;
- };
-
- nau8822: nau8822@1a {
- compatible = "nuvoton,nau8822";
- #sound-dai-cells = <1>;
- reg = <0x1a>;
- };
-
- gpio@50 {
- compatible = "nxp,pca9670";
- #gpio-cells = <2>;
- gpio-controller;
- reg = <0x50>;
- };
-
- rtc@51 {
- compatible = "nxp,pcf2129", "nxp,pcf2127";
- reg = <0x51>;
- };
-
- hwmon@52 {
- compatible = "tp,bm_mitx_hwmon";
- reg = <0x52>;
- };
-
- eeprom@53 {
- compatible = "atmel,24c32";
- pagesize = <32>;
- reg = <0x53>;
- };
-
- ps2port@54 {
- compatible = "tp,tp_serio";
- reg = <0x54>;
- interrupt-parent = <&porta>;
- interrupts = <14 8>;
- };
-};
-
-&i2c1 {
- status = "okay";
-};
-
-&i2s {
- status = "okay";
- system-clock-frequency = <12000000>;
- #sound-dai-cells = <0>;
-};
-
-&mdio0 {
- status = "disabled";
-};
-
-&mmc0 {
- status = "okay";
- disable-wp;
- bus-width = <4>;
- max-clock = <25000000>;
-};
-
-&pcie0 {
- status = "okay";
- reset-gpios = <&porta 6 GPIO_ACTIVE_LOW>;
-};
-
-&pcie2 {
- status = "okay";
- reset-gpios = <&porta 3 GPIO_ACTIVE_LOW>;
-};
-
-&pcie_lcru {
- status = "okay";
-};
-
-&porta {
- pcieclk {
- gpio-hog;
- gpios = <1 GPIO_ACTIVE_LOW>;
- output-high;
- line-name = "pcie-x8-clock";
- };
-};
-
-&pvt0 {
- status = "okay";
-};
-
-&pvt1 {
- status = "okay";
-};
-
-&pvt2 {
- status = "okay";
-};
-
-&pvt3 {
- status = "okay";
-};
-
-&pvt_mali {
- status = "okay";
-};
-
-&sata0 {
- status = "okay";
-};
-
-&sata1 {
- status = "okay";
-};
-
-&smbus0 {
- status = "okay";
-};
-
-&smbus1 {
- status = "okay";
-};
-
-&spi0 {
- num-cs = <4>;
- cs-gpios = <0>;
- status = "okay";
-};
-
-&timer1 {
- status = "okay";
-};
-
-&timer2 {
- status = "okay";
-};
-
-&timer3 {
- status = "okay";
-};
-
-&timer4 {
- status = "okay";
-};
-
-&uart0 {
- status = "okay";
-};
-
-&uart1 {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&vdec {
- status = "okay";
-};
-
-&vdu1 {
- status = "okay";
-};
diff --git a/arch/arm64/boot/dts/baikal/bm-mbm10.dts b/arch/arm64/boot/dts/baikal/bm-mbm10.dts
deleted file mode 100644
index 8e02d3e08f3e..000000000000
--- a/arch/arm64/boot/dts/baikal/bm-mbm10.dts
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device tree source for MBM 1.0 compatible boards:
- * - TP-TF307-MB-A0 Rev.1.0 (BM1BM1-A)
- * - TF307-MB-S-C Rev.3.0
- *
- * Copyright (C) 2021 Baikal Electronics, JSC
- */
-
-/dts-v1/;
-
-#include "bm-mbm.dtsi"
-
-/ {
- sound {
- simple-audio-card,hp-det-gpio = <&porta 27 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&gmac0 {
- status = "okay";
- snps,reset-gp-out;
- snps,reset-active-low;
-};
-
-&gmac1 {
- status = "okay";
- snps,reset-gp-out;
- snps,reset-active-low;
-};
diff --git a/arch/arm64/boot/dts/baikal/bm-mbm20.dts b/arch/arm64/boot/dts/baikal/bm-mbm20.dts
deleted file mode 100644
index 1c0a459a2781..000000000000
--- a/arch/arm64/boot/dts/baikal/bm-mbm20.dts
+++ /dev/null
@@ -1,102 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device tree source for MBM 2.0 compatible boards:
- * - TF307-MB-S-D Rev.4.0 (BM1BM1-D)
- *
- * Copyright (C) 2021 Baikal Electronics, JSC
- */
-
-/dts-v1/;
-
-#include <dt-bindings/input/input.h>
-#include "bm-mbm.dtsi"
-
-/ {
- panel {
- /* In order to utilize LVDS LCD panel, make sure that
- status is "okay" along with &vdu0 status (see below). */
- status = "disabled";
- compatible = "panel-lvds";
- width-mm = <223>;
- height-mm = <125>;
- data-mapping = "vesa-24";
- panel-timing {
- /* 1920x1080 @ 60 Hz */
- clock-frequency = <148500000>;
- hactive = <1920>;
- vactive = <1080>;
- hsync-len = <44>;
- hfront-porch = <88>;
- hback-porch = <148>;
- vsync-len = <5>;
- vfront-porch = <4>;
- vback-porch = <36>;
- };
- port {
- panel0_lvds0: endpoint@0 {
- remote-endpoint = <&vdu_lvds0_pads>;
- };
- panel0_lvds1: endpoint@1 {
- remote-endpoint = <&vdu_lvds1_pads>;
- };
- };
- };
-
- buttons-backlight {
- compatible = "gpio-keys";
- autorepeat;
- button-brightness-down {
- label = "Brightness Down Button";
- linux,code = <KEY_BRIGHTNESSDOWN>;
- gpios = <&porta 18 GPIO_ACTIVE_LOW>;
- debounce-interval = <50>;
- };
- button-brightness-up {
- label = "Brightness Up Button";
- linux,code = <KEY_BRIGHTNESSUP>;
- gpios = <&porta 17 GPIO_ACTIVE_LOW>;
- debounce-interval = <50>;
- };
- button-brightness-toggle {
- label = "Brightness Toggle Button";
- linux,code = <KEY_BRIGHTNESS_TOGGLE>;
- gpios = <&porta 31 GPIO_ACTIVE_LOW>;
- debounce-interval = <50>;
- };
- };
-
- sound {
- simple-audio-card,hp-det-gpio = <&porta 29 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&gmac0 {
- status = "okay";
- snps,reset-gpios = <&porta 19 GPIO_ACTIVE_LOW>;
-};
-
-&gmac1 {
- status = "okay";
- snps,reset-gpios = <&porta 20 GPIO_ACTIVE_LOW>;
-};
-
-&vdu0 {
- /* In order to utilize LVDS LCD panel, make sure that
- status is "okay" along with panel status (see above). */
- status = "disabled";
- enable-gpios = <&porta 16 GPIO_ACTIVE_LOW>;
- backlight {
- min-brightness-level = <10>;
- default-brightness-level = <60>;
- brightness-level-step = <2>;
- pwm-frequency = <20000>;
- };
- port {
- vdu_lvds0_pads: endpoint@0 {
- remote-endpoint = <&panel0_lvds0>;
- };
- vdu_lvds1_pads: endpoint@1 {
- remote-endpoint = <&panel0_lvds1>;
- };
- };
-};
diff --git a/arch/arm64/boot/dts/baikal/bm-qemu.dts b/arch/arm64/boot/dts/baikal/bm-qemu.dts
deleted file mode 100644
index c6350c0aaeb5..000000000000
--- a/arch/arm64/boot/dts/baikal/bm-qemu.dts
+++ /dev/null
@@ -1,163 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device tree source for Baikal-M software emulator (QEMU) platform
- * Copyright (C) 2018-2021 Baikal Electronics, JSC
- */
-
-/dts-v1/;
-
-#include "bm1000.dtsi"
-
-/*
- * Device "flash@0" was added to allow UEFI to boot on emulator.
- * TODO: the tree should be replaced by actual Baikal-M component tree
- */
-
-/ {
- model = "Baikal Electronics Baikal-M virtual platform";
- compatible = "baikal,baikal-m";
- #address-cells = <2>;
- #size-cells = <2>;
-
- chosen {
- stdout-path = "serial0:115200n8";
- bootargs = "root=/dev/ram rw rootwait console=ttyS0,115200n8 earlyprintk=uart8250,mmio32,0x20230000,115200";
- };
-
- memory@80000000 {
- device_type = "memory";
- /* 16GB */
- reg = <0x00000000 0x80000000 0x0 0x80000000
- 0x00000008 0x80000000 0x1 0x80000000>;
- };
-
- /* XXX: Temporary fix for qemu to work */
- /* Device is necessary for UEFI to boot on QEMU, need to replace it with something later */
- flash@0 {
- compatible = "cfi-flash";
- reg = <0x0 0x4000000 0x0 0x4000000>;
- bank-width = <0x4>;
- };
-
- panel: panel {
- compatible = "auo,b133htn01"; /* 1920x1080 */
- /*compatible = "auo,b133xtn01; /* 1366x768 */
- /*compatible = "auo,b101aw03"; /* 1024x600 */
- /*compatible = "innolux,g121x1-l03"; /* 1024x768 */
- /*compatible = "auo,b101ean01"; /* 1280x800 */
-
- port {
- lcd_panel: endpoint {
- remote-endpoint = <&vdu_pads>;
- };
- };
- };
-
- /*panel_hdmi: panel {
- compatible = "edt,et057090dhu";
-
- port {
- lcd_hdmi_panel: endpoint {
- remote-endpoint = <&vdu_hdmi_pads>;
- };
- };
- };*/
-};
-
-&gmac0 {
- status = "okay";
-};
-
-&gmac1 {
- status = "okay";
-};
-
-&sata0 {
- status = "okay";
-};
-
-&sata1 {
- status = "okay";
-};
-
-&spi0 {
- num-cs = <6>;
- status = "okay";
-
- /* SPI flash chip #1 */
- flash0: m25p80@0 {
- compatible = "micron,n25q256a", "jedec,spi-nor";
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <50000000>;
- status = "okay";
-
- /* Flash chip0 partitions */
- mtd0@0 {
- label = "fip";
- reg = <0x00000000 0x00400000>;
- read-only;
- };
-
- mtd1@400000 {
- label = "env";
- reg = <0x00400000 0x00100000>;
- };
-
- mtd2@500000 {
- label = "kernel";
- reg = <0x00500000 0x00400000>;
- };
-
- mtd3@900000 {
- label = "rootfs";
- reg = <0x00900000 0x00800000>;
- };
-
- mtd4@1100000 {
- label = "data0";
- reg = <0x01100000 0x00f00000>;
- };
- };
-
- /* SPI flash chip #2 */
- flash1: m25p80@1 {
- compatible = "micron,n25q256a", "jedec,spi-nor";
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <50000000>;
- status = "okay";
-
- /* Flash chip1 partitions */
- mtd0@0 {
- label = "fip_backup";
- reg = <0x00000000 0x00400000>;
- read-only;
- };
-
- mtd1@400000 {
- label = "env_backup";
- reg = <0x00400000 0x00100000>;
- read-only;
- };
-
- mtd2@500000 {
- label = "data1";
- reg = <0x00500000 0x01b00000>;
- };
- };
-};
-
-&uart0 {
- status = "okay";
-};
-
-&vdu0 {
- port {
- vdu_pads: endpoint {
- remote-endpoint = <&lcd_panel>;
- };
- };
-};
diff --git a/arch/arm64/boot/dts/baikal/bm1000-clocks.dtsi b/arch/arm64/boot/dts/baikal/bm1000-clocks.dtsi
deleted file mode 100644
index 3c0d7de3c576..000000000000
--- a/arch/arm64/boot/dts/baikal/bm1000-clocks.dtsi
+++ /dev/null
@@ -1,363 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device tree include file for BE-M1000 SoC clocks
- * Copyright (C) 2017-2021 Baikal Electronics, JSC
- */
-
-/ {
- /* external oscillator */
- osc25: oscillator25 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- clock-output-names = "osc25";
- };
-
- /* external oscillator */
- osc27: oscillator27 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <27000000>;
- clock-output-names = "osc27";
- };
-
- cmu_cluster0: cmu_cluster0 {
- compatible = "baikal,cmu";
- clock-output-names = "baikal-ca57_cmu0";
- #clock-cells = <0>;
- clocks = <&osc25>;
- cmu-id = <0x28000000>;
- max = <1500000000>;
- min = <500000000>;
- clock-frequency = <1500000000>;
- };
-
- cmu_cluster1: cmu_cluster1 {
- compatible = "baikal,cmu";
- clock-output-names = "baikal-ca57_cmu1";
- #clock-cells = <0>;
- clocks = <&osc25>;
- cmu-id = <0xc000000>;
- max = <1500000000>;
- min = <500000000>;
- clock-frequency = <1500000000>;
- };
-
- cmu_cluster2: cmu_cluster2 {
- compatible = "baikal,cmu";
- clock-output-names = "baikal-ca57_cmu2";
- #clock-cells = <0>;
- clocks = <&osc25>;
- cmu-id = <0xa000000>;
- max = <1500000000>;
- min = <500000000>;
- clock-frequency = <1500000000>;
- };
-
- cmu_cluster3: cmu_cluster3 {
- compatible = "baikal,cmu";
- clock-output-names = "baikal-ca57_cmu3";
- #clock-cells = <0>;
- clocks = <&osc25>;
- cmu-id = <0x26000000>;
- max = <1500000000>;
- min = <500000000>;
- clock-frequency = <1500000000>;
- };
-
- cmu0_avlsp: cmu0_avlsp {
- compatible = "baikal,cmu";
- #clock-cells = <1>;
- clock-output-names = "baikal-avlsp_cmu0";
- clock-names =
- "gpio", // <0>
- "uart1", // <1>
- "uart2", // <2>
- "apb", // <3>
- "spi", // <4>
- "espi", // <5>
- "i2c1", // <6>
- "i2c2", // <7>
- "timer1", // <8>
- "timer2", // <9>
- "timer3", // <10>
- "timer4", // <11>
- "dmac", // <12>
- "smbus1", // <13>
- "smbus2", // <14>
- "hda_sys_clk", // <15>
- "hda_clk48", // <16>
- "mshc_axi", // <17>
- "mshc_ahb", // <18>
- "mshc_tx_x2", // <19>
- "mshc_b", // <20>
- "mshc_tm", // <21>
- "mshc_cqetm", // <22>
- "hwa_clu", // <23>
- "hwa_clu_hf", // <24>
- "hwa_axi", // <25>
- "vdu_axi", // <26>
- "smmu"; // <27>
- clock-indices =
- <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, <10>,
- <11>, <12>, <13>, <14>, <15>, <16>, <17>, <18>, <19>,
- <20>, <21>, <22>, <23>, <24>, <25>, <26>, <27>;
- clocks = <&osc25>;
- cmu-id = <0x20000000>;
- max = <2100000000>;
- min = <800000>;
- clock-frequency = <1200000000>;
- };
-
- cmu1_avlsp: cmu1_avlsp {
- compatible = "baikal,cmu";
- clock-output-names = "baikal-avlsp_cmu1";
- #clock-cells = <0>;
- clocks = <&osc27>;
- cmu-id = <0x20010000>;
- max = <2100000000>;
- min = <13500000>;
- clock-frequency = <1039500000>;
- };
-
- cmu_mali: cmu_mali {
- compatible = "baikal,cmu";
- clock-output-names = "baikal-mali-cmu";
- #clock-cells = <0>;
- clocks = <&osc25>;
- clock-names = "aclk";
- cmu-id = <0x2a000000>;
- max = <800000000>;
- min = <400000000>;
- clock-frequency = <750000000>;
- };
-
- cmu0_xgbe: cmu0_xgbe {
- compatible = "baikal,cmu";
- clock-output-names = "baikal-xgbe-cmu0";
- #clock-cells = <1>;
- clocks = <&osc25>;
- clock-names = "csr50mhz", "gmac0_tx2", "gmac1_tx2", "hdmi_aclk", "isfr";
- clock-indices = <0>, <10>, <13>, <15>, <17>;
- cmu-id = <0x30000000>;
- max = <1250000000>;
- min = <50000000>;
- clock-frequency = <1250000000>;
- };
-
- cmu1_xgbe: cmu1_xgbe {
- compatible = "baikal,cmu";
- clock-output-names = "baikal-xgbe-cmu1";
- #clock-cells = <1>;
- clocks = <&osc27>;
- clock-indices = <0>;
- clock-names = "pixelclk";
- cmu-id = <0x30010000>;
- max = <600000000>;
- min = <13500000>;
- clock-frequency = <25250000>;
- };
-
- clocks {
- cpu_clk: cpu_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1500000000>;
- clock-output-names = "cpuclk";
- };
-
- apb_clk: apb_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- clock-output-names = "apb_pclk";
- };
-
- uart_clk: uart_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <7273800>;
- clock-output-names = "soc_uartclk";
- };
-
- i2c_clk: i2c_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- clock-output-names = "soc_i2cclk";
- };
-
- smbus_clk: smbus_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <50000000>;
- clock-output-names = "soc_smbusclk";
- };
-
- timer1_clk: timer1_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <50000000>;
- clock-output-names = "soc_timer1clk";
- };
-
- timer2_clk: timer2_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <50000000>;
- clock-output-names = "soc_timer2clk";
- };
-
- timer3_clk: timer3_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <50000000>;
- clock-output-names = "soc_timer3clk";
- };
-
- timer4_clk: timer4_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <50000000>;
- clock-output-names = "soc_timer4clk";
- };
-
- gpio_clk: gpio_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1000000>;
- clock-output-names = "soc_gpioclk";
- };
-
- spi_clk: spi_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <50000000>;
- clock-output-names = "soc_spiclk";
- };
-
- soc_ethclk: ethclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <50000000>;
- clock-output-names = "eth_clk";
- };
-
- soc_xgbeclk: xgbeclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <156250000>;
- clock-output-names = "xgbe_clk";
- };
-
- soc_smc50mhz: clk50mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <50000000>;
- clock-output-names = "smc_clk";
- };
-
- soc_faxiclk: refclk400mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <400000000>;
- clock-output-names = "faxi_clk";
- };
-
- soc_tmp_clk: refclkXXXmhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- clock-output-names = "tmpclk";
- };
-
- gpu_clk: gpu_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <750000000>;
- clock-output-names = "gpuclk";
- };
- gpu_opp_table: opp_table_gpu {
- compatible = "operating-points-v2", "operating-points-v2-mali";
-
- opp-400000000 {
- opp-hz = /bits/ 64 <400000000>;
- clock-latency-ns = <10000000>;
- };
- opp-450000000 {
- opp-hz = /bits/ 64 <450000000>;
- clock-latency-ns = <10000000>;
- };
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- clock-latency-ns = <10000000>;
- };
- opp-550000000 {
- opp-hz = /bits/ 64 <550000000>;
- clock-latency-ns = <10000000>;
- };
- opp-600000000 {
- opp-hz = /bits/ 64 <600000000>;
- clock-latency-ns = <10000000>;
- };
- opp-650000000 {
- opp-hz = /bits/ 64 <650000000>;
- clock-latency-ns = <10000000>;
- };
- opp-700000000 {
- opp-hz = /bits/ 64 <700000000>;
- clock-latency-ns = <10000000>;
- };
- opp-750000000 {
- opp-hz = /bits/ 64 <750000000>;
- clock-latency-ns = <10000000>;
- };
- };
-
- clk_ahb: clk_ahb {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- clock-output-names = "clk_ahb";
- };
-
- clk_xin: clk_xin {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- clock-output-names = "clk_xin";
- };
-
- cortex_cmu: cmu@cortex {
- compatible = "baikal,cmu-device-clock";
- #clock-cells = <1>;
- clock-frequency = <1000000000>;
- clock-output-names = "baikal-cmu";
- };
-
- avlsp_cmu1: cmu1@avlsp {
- compatible = "baikal,cmu-device-clock";
- #clock-cells = <1>;
- clock-indices = <26>;
- clock-frequency = <240000000>;
- clock-output-names = "baikal-cmu";
- };
-
- usb_clk: usb_clk@1f04d074 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-names = "usbclk";
- clock-frequency = <500000000>;
- clock-output-names = "usbclk";
- };
-
- cmu1_avlsp_div7: cmu1_avlsp_div7 {
- compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock";
- clocks = <&cmu1_avlsp>;
- #clock-cells = <0>;
- clock-div = <7>;
- clock-mult = <1>;
- clock-output-names = "lvds_clk";
- };
- };
-};
diff --git a/arch/arm64/boot/dts/baikal/bm1000-cpufreq.dtsi b/arch/arm64/boot/dts/baikal/bm1000-cpufreq.dtsi
deleted file mode 100644
index 6303c6f00611..000000000000
--- a/arch/arm64/boot/dts/baikal/bm1000-cpufreq.dtsi
+++ /dev/null
@@ -1,249 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device tree include file for BE-M1000 SoC CPU frequencies
- * Copyright (C) 2020-2021 Baikal Electronics, JSC
- */
-
-/ {
- cpufreq {
- cluster0_opp: opp_table0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-1500000000 {
- opp-hz = /bits/ 64 <1500000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-1400000000 {
- opp-hz = /bits/ 64 <1400000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-1300000000 {
- opp-hz = /bits/ 64 <1300000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-1100000000 {
- opp-hz = /bits/ 64 <1100000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-900000000 {
- opp-hz = /bits/ 64 <900000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-700000000 {
- opp-hz = /bits/ 64 <700000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-600000000 {
- opp-hz = /bits/ 64 <600000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- clock-latency-ns = <10000000>;
- };
- };
-
- cluster1_opp: opp_table1 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-1500000000 {
- opp-hz = /bits/ 64 <1500000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-1400000000 {
- opp-hz = /bits/ 64 <1400000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-1300000000 {
- opp-hz = /bits/ 64 <1300000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-1100000000 {
- opp-hz = /bits/ 64 <1100000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-900000000 {
- opp-hz = /bits/ 64 <900000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-700000000 {
- opp-hz = /bits/ 64 <700000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-600000000 {
- opp-hz = /bits/ 64 <600000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- clock-latency-ns = <10000000>;
- };
- };
-
- cluster2_opp: opp_table2 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-1500000000 {
- opp-hz = /bits/ 64 <1500000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-1400000000 {
- opp-hz = /bits/ 64 <1400000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-1300000000 {
- opp-hz = /bits/ 64 <1300000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-1100000000 {
- opp-hz = /bits/ 64 <1100000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-900000000 {
- opp-hz = /bits/ 64 <900000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-700000000 {
- opp-hz = /bits/ 64 <700000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-600000000 {
- opp-hz = /bits/ 64 <600000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- clock-latency-ns = <10000000>;
- };
- };
-
- cluster3_opp: opp_table3 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-1500000000 {
- opp-hz = /bits/ 64 <1500000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-1400000000 {
- opp-hz = /bits/ 64 <1400000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-1300000000 {
- opp-hz = /bits/ 64 <1300000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-1100000000 {
- opp-hz = /bits/ 64 <1100000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-900000000 {
- opp-hz = /bits/ 64 <900000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-700000000 {
- opp-hz = /bits/ 64 <700000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-600000000 {
- opp-hz = /bits/ 64 <600000000>;
- clock-latency-ns = <10000000>;
- };
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- clock-latency-ns = <10000000>;
- };
- };
- };
-};
diff --git a/arch/arm64/boot/dts/baikal/bm1000.dtsi b/arch/arm64/boot/dts/baikal/bm1000.dtsi
deleted file mode 100644
index ee68b7d1e316..000000000000
--- a/arch/arm64/boot/dts/baikal/bm1000.dtsi
+++ /dev/null
@@ -1,1060 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device tree include file for BE-M1000 SoC
- * Copyright (C) 2017-2021 Baikal Electronics, JSC
- */
-
-#include "bm1000-clocks.dtsi"
-#include "bm1000-cpufreq.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/*
- * ARM GICv3 bindings assume interrupts (in each range) counting from 0:
- * PPI: 0..15
- * SPI: 0..987
- * Baikal-M documentation ("Interrupt map") places all interrupts into the
- * linear map: SGI(0..15), PPI(16..31), SPI(32-1019).
- * So real interrupt IDs in this device tree must be calculated as follows:
- * PPI_real = PPI_from_documentation - 16
- * SPI_real = SPI_from_documentation - 32
- */
-
-/ {
- compatible = "baikal,arm", "baikal,baikal-m-soc", "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&gic>;
-
- aliases {
- ethernet1 = &gmac0;
- ethernet2 = &gmac1;
- ethernet3 = &xgmac0;
- ethernet4 = &xgmac1;
- gic = &gic;
- gpio0 = &gpio;
- hda = &hda;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2s = &i2s;
- memory-controller1 = &ddr1;
- memory-controller2 = &ddr2;
- mmc0 = &mmc0;
- pvt0 = &pvt0;
- pvt1 = &pvt1;
- pvt2 = &pvt2;
- pvt3 = &pvt3;
- pvt_mali = &pvt_mali;
- sata0 = &sata0;
- sata1 = &sata1;
- serial0 = &uart0;
- serial1 = &uart1;
- smbus0 = &smbus0;
- smbus1 = &smbus1;
- spi = &spi0;
- ssi0 = &spi0;
- timer1 = &timer1;
- timer2 = &timer2;
- timer3 = &timer3;
- timer4 = &timer4;
- usb2 = &usb2;
- usb3 = &usb3;
- vdec = &vdec;
- vdu_lvds = &vdu0;
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
- };
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- /* Do not use 'cpu-map'. It leads to wrong topology. */
-
- CPU0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x0>;
- enable-method = "psci";
- i-cache-size = <0xc000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- clocks = <&cmu_cluster0>;
- next-level-cache = <&cluster0_l2>;
- clock-names = "baikal-ca57_cmu";
- operating-points-v2 = <&cluster0_opp>;
- };
-
- CPU1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x1>;
- enable-method = "psci";
- i-cache-size = <0xc000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- clocks = <&cmu_cluster0>;
- next-level-cache = <&cluster0_l2>;
- clock-names = "baikal-ca57_cmu";
- operating-points-v2 = <&cluster0_opp>;
- };
-
- CPU2: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x100>;
- enable-method = "psci";
- i-cache-size = <0xc000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- clocks = <&cmu_cluster1>;
- next-level-cache = <&cluster1_l2>;
- clock-names = "baikal-ca57_cmu";
- operating-points-v2 = <&cluster1_opp>;
- };
-
- CPU3: cpu@101 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x101>;
- enable-method = "psci";
- i-cache-size = <0xc000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- clocks = <&cmu_cluster1>;
- next-level-cache = <&cluster1_l2>;
- clock-names = "baikal-ca57_cmu";
- operating-points-v2 = <&cluster1_opp>;
- };
-
- CPU4: cpu@200 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x200>;
- enable-method = "psci";
- i-cache-size = <0xc000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- clocks = <&cmu_cluster2>;
- next-level-cache = <&cluster2_l2>;
- clock-names = "baikal-ca57_cmu";
- operating-points-v2 = <&cluster2_opp>;
- };
-
- CPU5: cpu@201 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x201>;
- enable-method = "psci";
- i-cache-size = <0xc000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- clocks = <&cmu_cluster2>;
- next-level-cache = <&cluster2_l2>;
- clock-names = "baikal-ca57_cmu";
- operating-points-v2 = <&cluster2_opp>;
- };
-
- CPU6: cpu@300 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x300>;
- enable-method = "psci";
- i-cache-size = <0xc000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- clocks = <&cmu_cluster3>;
- next-level-cache = <&cluster3_l2>;
- clock-names = "baikal-ca57_cmu";
- operating-points-v2 = <&cluster3_opp>;
- };
-
- CPU7: cpu@301 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x301>;
- enable-method = "psci";
- i-cache-size = <0xc000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <256>;
- clocks = <&cmu_cluster3>;
- next-level-cache = <&cluster3_l2>;
- clock-names = "baikal-ca57_cmu";
- operating-points-v2 = <&cluster3_opp>;
- };
-
- cluster0_l2: l2-cache0 {
- compatible = "cache";
- cache-size = <0x100000>;
- cache-line-size = <64>;
- cache-sets = <1024>;
- cache-unified;
- cache-level = <2>;
- next-level-cache = <&l3>;
- };
-
- cluster1_l2: l2-cache1 {
- compatible = "cache";
- cache-size = <0x100000>;
- cache-line-size = <64>;
- cache-sets = <1024>;
- cache-unified;
- cache-level = <2>;
- next-level-cache = <&l3>;
- };
-
- cluster2_l2: l2-cache2 {
- compatible = "cache";
- cache-size = <0x100000>;
- cache-line-size = <64>;
- cache-sets = <1024>;
- cache-unified;
- cache-level = <2>;
- next-level-cache = <&l3>;
- };
-
- cluster3_l2: l2-cache3 {
- compatible = "cache";
- cache-size = <0x100000>;
- cache-line-size = <64>;
- cache-sets = <1024>;
- cache-unified;
- cache-level = <2>;
- next-level-cache = <&l3>;
- };
-
- l3: l3-cache {
- cache-size = <0x800000>;
- cache-unified;
- cache-level = <3>;
- };
- };
-
- pmu {
- compatible = "arm,cortex-a57-pmu";
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- /* DDR0 (e200000, 10000, SPI_161-166_?) */
- ddr1: memory-controller1@e200000 {
- compatible = "be,emc", "be,memory-controller";
- reg = <0x0 0x0e200000 0x0 0x10000>;
- interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, /* ddr dfi alert err */
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, /* ddr ecc corrected err */
- <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, /* ddr ecc uncorrected err */
- <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, /* ddr sbr done */
- <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, /* ddr ecc corrected err fault */
- <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; /* ddr ecc uncorrected err fault */
- clocks = <&soc_smc50mhz>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
-
- /* DDR1 (22200000, 10000, SPI_171-176_?) */
- ddr2: memory-controller2@22200000 {
- compatible = "be,emc", "be,memory-controller";
- reg = <0x0 0x22200000 0x0 0x10000>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, /* ddr dfi alert err */
- <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, /* ddr ecc corrected err */
- <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, /* ddr ecc uncorrected err */
- <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* ddr sbr done */
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* ddr ecc corrected err fault */
- <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; /* ddr ecc uncorrected err fault */
- clocks = <&soc_smc50mhz>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
-
- pcie_lcru: lcru@2000000 {
- compatible = "syscon";
- reg = <0x0 0x2000000 0x0 0x80000>;
- /*big-endian;*/
- status = "disabled";
- };
-
- pcie0: pcie@2200000 { /* PCIe x4 #0 */
- compatible = "baikal,pcie-m", "snps,dw-pcie";
- reg = <0x0 0x02200000 0x0 0x1000>, /* RC config space */
- <0x0 0x40100000 0x0 0x100000>; /* PCI config space */
- reg-names = "dbi", "config";
- interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, /* AER */
- <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; /* MSI */
- #interrupt-cells = <1>;
- baikal,pcie-lcru = <&pcie_lcru 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- ranges = <0x81000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, /* I/O */
- <0x82000000 0x0 0x40000000 0x4 0x00000000 0x0 0x40000000>; /* 32b non-prefetchable memory */
- msi-parent = <&its 0x0>;
- msi-map = <0x0 &its 0x0 0x10000>;
- num-lanes = <4>;
- num-viewport = <4>;
- bus-range = <0x0 0xff>;
- status = "disabled";
- };
-
- pcie1: pcie@2210000 { /* PCIe x4 #1 */
- compatible = "baikal,pcie-m", "snps,dw-pcie";
- reg = <0x0 0x02210000 0x0 0x1000>, /* RC config space */
- <0x0 0x50100000 0x0 0x100000>; /* PCI config space */
- reg-names = "dbi", "config";
- interrupts = <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, /* AER */
- <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; /* MSI */
- #interrupt-cells = <1>;
- baikal,pcie-lcru = <&pcie_lcru 1>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- ranges = <0x81000000 0x0 0x00100000 0x0 0x50000000 0x0 0x100000>, /* I/O */
- <0x82000000 0x0 0x40000000 0x5 0x00000000 0x0 0x40000000>; /* 32b non-prefetchable memory */
- msi-parent = <&its 0x0>;
- msi-map = <0x0 &its 0x0 0x10000>;
- num-lanes = <4>;
- num-viewport = <4>;
- bus-range = <0x0 0xff>;
- status = "disabled";
- };
-
- pcie2: pcie@2220000 { /* PCIe x8 */
- compatible = "baikal,pcie-m", "snps,dw-pcie";
- reg = <0x0 0x02220000 0x0 0x1000>, /* RC config space */
- <0x0 0x60000000 0x0 0x100000>; /* PCI config space */
- reg-names = "dbi", "config";
- interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, /* AER */
- <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; /* MSI */
- #interrupt-cells = <1>;
- baikal,pcie-lcru = <&pcie_lcru 2>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- ranges = <0x81000000 0x0 0x00200000 0x0 0x60100000 0x0 0x100000>, /* I/O */
- <0x82000000 0x0 0x80000000 0x6 0x00000000 0x0 0x80000000>; /* 32b non-prefetchable memory */
- msi-parent = <&its 0x0>;
- msi-map = <0x0 &its 0x0 0x10000>;
- num-lanes = <8>;
- num-viewport = <4>;
- bus-range = <0x0 0xff>;
- status = "disabled";
- };
-
- ccn: ccn@9000000 {
- compatible = "arm,ccn-504";
- reg = <0x0 0x9000000 0 0x1000000>;
- interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pvt0: pvt0@28200000 {
- compatible = "baikal,pvt";
- reg = <0x0 0x28200000 0x0 0x10000>;
- pvt_id = <0>;
- interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- pvt1: pvt1@c200000 {
- compatible = "baikal,pvt";
- reg = <0x0 0xc200000 0x0 0x10000>;
- pvt_id = <1>;
- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- pvt2: pvt2@a200000 {
- compatible = "baikal,pvt";
- reg = <0x0 0xa200000 0x0 0x10000>;
- pvt_id = <2>;
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- pvt3: pvt3@26200000 {
- compatible = "baikal,pvt";
- reg = <0x0 0x26200000 0x0 0x10000>;
- pvt_id = <3>;
- interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- pvt_mali: pvt_mali@2a060000 {
- compatible = "baikal,pvt";
- reg = <0x0 0x2a060000 0x0 0x10000>;
- pvt_id = <4>;
- interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- /* AVLSP: GPIO32 (20200000, 10000, SPI_131_H) */
- gpio: gpio@20200000 {
- compatible = "snps,dw-apb-gpio";
- reg = <0x0 0x20200000 0x0 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
-
- porta: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- #gpio-cells = <2>;
- gpio-controller;
- snps,nr-gpios = <32>;
- reg = <0>;
- #interrupt-cells = <2>;
- interrupt-controller;
- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- /* AVLSP: SPI (20210000, 10000, SPI_132_H) */
- spi0: spi@20210000 {
- compatible = "snps,dw-apb-ssi", "snps,dw-spi";
- reg = <0x0 0x20210000 0x0 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cmu0_avlsp 4>;
- clock-names = "soc_spiclk";
- status = "disabled";
- };
-
- /* AVLSP: I2S (20220000, 1000, SPI_136-139_H) */
- i2s: i2s@20220000 {
- compatible = "snps,designware-i2s";
- reg = <0x0 0x20220000 0x0 0x10000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* rx_da */
- <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, /* rx_or */
- <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, /* tx_emp */
- <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; /* tx_or */
- /*dmas = <&dma 2>, <&dma 3>;*/
- /*dma-names = "tx", "rx";*/
- /*#sound-dai-cells = <0>;*/
- clocks = <&soc_tmp_clk>;
- clock-names = "i2sclk";
- status = "disabled";
- };
-
- /* AVLSP: UART1 (20230000, 10000, SPI_133_H) */
- uart0: serial0@20230000 {
- compatible = "snps,dw-apb-uart"; /* "snps,uart-16550-compatible" */
- reg = <0x0 0x20230000 0x0 0x10000>;
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&cmu0_avlsp 1>, <&apb_clk>;
- clock-names = "soc_uartclk", "apb_pclk";
- /*dcd-override;*/
- /*dsr-override;*/
- /*cts-override;*/
- /*ri-override;*/
- status = "disabled";
- };
-
- /* AVLSP: UART2 (20240000, 10000, SPI_134_H) */
- uart1: serial1@20240000 {
- compatible = "snps,dw-apb-uart"; /* "snps,uart-16550-compatible" */
- reg = <0x0 0x20240000 0x0 0x10000>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&cmu0_avlsp 2>, <&apb_clk>;
- clock-names = "soc_uartclk", "apb_pclk";
- status = "disabled";
- };
-
- /* AVLSP: I2C1 (20250000, 10000, SPI_140_H) */
- i2c0: i2c0@20250000 {
- compatible = "snps,designware-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x20250000 0x0 0x10000>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- i2c-sda-hold-time-ns = <500>;
- clock-frequency = <400000>;
- clocks = <&i2c_clk>;
- clock-names = "soc_i2cclk";
- status = "disabled";
- };
-
- /* AVLSP: I2C2 (20260000, 10000, SPI_141_H) */
- i2c1: i2c1@20260000 {
- compatible = "snps,designware-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x20260000 0x0 0x10000>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- i2c-sda-hold-time-ns = <500>;
- clock-frequency = <400000>;
- clocks = <&i2c_clk>;
- clock-names = "soc_i2cclk";
- status = "disabled";
- };
-
- /* AVLSP: SMBus1 (20270000, 10000, SPI_142_?) */
- smbus0: smbus0@20270000 {
- compatible = "be,smbus";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x20270000 0x0 0x10000>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <100000>;
- clocks = <&smbus_clk>;
- clock-names = "soc_smbusclk";
- status = "disabled";
- };
-
- /* AVLSP: SMBus2 (20280000, 10000, SPI_143_?) */
- smbus1: smbus1@20280000 {
- compatible = "be,smbus";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x20280000 0x0 0x10000>;
- interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <100000>;
- clocks = <&smbus_clk>;
- clock-names = "soc_smbusclk";
- status = "disabled";
- };
-
- /* AVLSP: Timers (20290000, 10000, SPI_127_L) */
- timer1: timer1@20290000 {
- compatible = "snps,dw-apb-timer-osc";
- reg = <0x0 0x20290000 0x0 0x14>;
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <50000000>;
- clocks = <&timer1_clk>;
- clock-names = "soc_timer1clk";
- status = "disabled";
- };
-
- /* AVLSP: Timers (20290000, 10000, SPI_128_L) */
- timer2: timer2@20290014 {
- compatible = "snps,dw-apb-timer-sp";
- reg = <0x0 0x20290014 0x0 0x14>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <50000000>;
- clocks = <&timer2_clk>;
- clock-names = "soc_timer2clk";
- status = "disabled";
- };
-
- /* AVLSP: Timers (20290000, 10000, SPI_129_L) */
- timer3: timer3@20290028 {
- compatible = "snps,dw-apb-timer-sp";
- reg = <0x0 0x20290028 0x0 0x14>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <50000000>;
- clocks = <&timer3_clk>;
- clock-names = "soc_timer3clk";
- status = "disabled";
- };
-
- /* AVLSP: Timers (20290000, 10000, SPI_130_L) */
- timer4: timer4@2029003c {
- compatible = "snps,dw-apb-timer-sp";
- reg = <0x0 0x2029003c 0x0 0x14>;
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <50000000>;
- clocks = <&timer4_clk>;
- clock-names = "soc_timer4clk";
- status = "disabled";
- };
-
- /* AVLSP: eSPI (202a0000, 10000, SPI_135_?) */
- espi0: espi0@202a0000 {
- compatible = "be,espi";
- reg = <0x0 0x202a0000 0x0 0x10000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cmu0_avlsp 5>;
- clock-names = "soc_espiclk";
- status = "disabled";
- /*
- * Block Configuration:
- * - master/slave
- * - 32-bit APB slave
- * - tx-fifo = rx-fifo = 256 byte
- * - 4 SPI IO channels
- * - 8 slave select IO channels
- * - DMA - missing
- * - M-flash controller - missing
- */
- };
-
- /* AVLSP: DMAC (202b0000, 10000, SPI_41-80_H) */
- lsdma: dma@202b0000 {
- compatible = "snps,dma-spear1340";
- reg = <0x0 0x202b0000 0x0 0x10000>;
- /* TODO: interrupts */
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- dma-channels = <8>;
- dma-requests = <16>;
- dma-masters = <2>;
- #dma-cells = <3>;
- chan_allocation_order = <1>;
- chan_priority = <1>;
- block_size = <0xfff>;
- data_width = <3 3 0 0>;
- clocks = <&soc_tmp_clk>;
- clock-names = "tmpclk";
- status = "disabled";
- };
-
- /* AVLSP: HDA (202c0000, 10000, SPI_86_H) */
- hda: hda@202c0000 {
- compatible = "be,cw-hda";
- reg = <0x0 0x202c0000 0x0 0x1000>;
- interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cmu0_avlsp 15>, <&cmu0_avlsp 16>;
- clock-names = "hda_sys_clk", "hda_clk48";
- status = "disabled";
- };
-
- /* AVLSP: VDU (202d0000, 10000, SPI_144-145_?) */
- vdu0: vdu_lvds@202d0000 {
- compatible = "baikal,vdu";
- reg = <0x0 0x202d0000 0x0 0x1000>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, /* VDU INTR */
- <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* VDU INTR_CDD */
- clocks = <&cmu1_avlsp_div7>;
- clock-names = "pclk";
- lvds-out;
- status = "disabled";
- };
-
- /* AVLSP: SD/eMMC (202e0000, 10000, SPI_83-84_H) */
- mmc0: mmc@202e0000 {
- compatible = "snps,dwcmshc-sdhci";
- reg = <0x0 0x202e0000 0x0 0x10000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "bus", "core";
- clocks = <&cmu0_avlsp 18>, <&cmu0_avlsp 19>;
- status = "disabled";
- };
-
- vdec: vdec@24200000 {
- compatible = "baikal,d5500-vxd";
- reg = <0x0 0x24200000 0x0 0x10000>;
- interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- gpu: gpu@2a200000 {
- compatible = "arm,mali-midgard", "arm,mali-t628";
- #cooling-cells = <2>; /* min followed by max */
- reg = <0x0 0x2a200000 0x0 0x4000>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "job", "mmu", "gpu";
- clocks = <&cmu_mali>;
- clock-names = "gpuclk";
- dma-coherent;
- operating-points-v2 = <&gpu_opp_table>;
- };
-
- /* USB MM: USB2 (2c400000, 100000, SPI_267-268_H, SPI_277_H) */
- usb2: usb2@2c400000 {
- compatible = "be,baikal-dwc3";
- status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- clocks = <&usb_clk>;
- clock-names = "usb";
- dma-coherent;
-
- dwc3@2c400000 {
- compatible = "snps,dwc3", "synopsys,dwc3", "generic-xhci";
- reg = <0x0 0x2c400000 0x0 0x100000>;
- interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- dma-coherent;
- maximum-speed = "high-speed";
- };
- };
-
- /* USB MM: USB3 (2c500000, 100000, SPI_269-276_H, SPI_278_H) */
- usb3: usb3@2c500000 {
- compatible = "be,baikal-dwc3";
- status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- clocks = <&usb_clk>;
- clock-names = "usb";
-
- dwc3@2c500000 {
- compatible = "snps,dwc3", "synopsys,dwc3", "generic-xhci";
- reg = <0x0 0x2c500000 0x0 0x100000>;
- interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- dma-coherent;
- };
- };
-
- /* USB MM: SATA0 (2c600000, 10000, SPI_265_H) */
- sata0: sata0@2c600000 {
- compatible = "snps,dwc-ahci", "generic-ahci";
- reg = <0x0 0x2c600000 0 0x10000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
- ports-implemented = <1>;
- dma-coherent;
- clocks = <&soc_faxiclk>;
- clock-names = "sataclk";
- status = "disabled";
- };
-
- /* USB MM: SATA1 (2c610000, 10000, SPI_266_H) */
- sata1: sata1@2c610000 {
- compatible = "snps,dwc-ahci", "generic-ahci";
- reg = <0x0 0x2c610000 0 0x10000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
- ports-implemented = <1>;
- dma-coherent;
- clocks = <&soc_faxiclk>;
- clock-names = "sataclk";
- status = "disabled";
- };
-
- /* DMA-330: DMAC ("secure", 2c620000, 10000, SPI_255-263_H) */
- /* ("non-secure", 2c630000, 10000, ?) */
- dma: dma@2c620000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0x2c620000 0 0x1000>;
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&soc_faxiclk>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
-
- gic: interrupt-controller@2d000000 {
- compatible = "arm,gic-v3";
- #interrupt-cells = <3>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- interrupt-controller;
- reg = <0x0 0x2d000000 0x0 0x10000>, /* GICD */
- <0x0 0x2d100000 0x0 0x200000>, /* GICR */
- <0x0 0x10200000 0x0 0x2000>, /* GICC */
- <0x0 0x10210000 0x0 0x1000>, /* GICH */
- <0x0 0x10220000 0x0 0x2000>; /* GICV */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-
- its: its@2d020000 {
- compatible = "arm,gic-v3-its";
- msi-controller;
- #msi-cells = <1>;
- reg = <0x0 0x2d020000 0x0 0x20000>; /* GITS */
- };
- };
-
- axi_gmac: stmmac-axi-config0 {
- snps,wr_osr_lmt = <0x0>;
- snps,rd_osr_lmt = <0x0>;
- snps,blen = <0 0 0 0 0 0 4>;
- };
-
- gmac0: eth0@30240000 {
- compatible = "be,dwmac", "snps,dwmac-3.710", "snps,dwmac";
- reg = <0x0 0x30240000 0x0 0x10000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- max-speed = <1000>;
- clocks = <&soc_ethclk>, <&cmu0_xgbe 10>;
- clock-names = "stmmaceth", "tx2_clk";
- mac-address = [ 00 00 00 00 00 00 ];
- local-mac-address = [ 00 00 00 00 00 00 ];
- phy-mode = "rgmii-id";
- phy-handle = <&gmac0_phy>;
- snps,fixed-burst;
- snps,axi-config = <&axi_gmac>;
- snps,no-pbl-x8;
- snps,txpbl = <4>;
- snps,rxpbl = <4>;
- snps,reset-delays-us = <0 10200 1000>;
- status = "disabled";
- dma-coherent;
-
- gmdio0: gmac0_mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- gmac0_phy: ethernet-phy@3 {
- compatible = "ethernet-phy-id0022.1620", "ethernet-phy-ieee802.3-c22";
- reg = <0x3>;
- txd0-skew-ps = <0>;
- txd1-skew-ps = <0>;
- txd2-skew-ps = <0>;
- txd3-skew-ps = <0>;
- txc-skew-ps = <0xff>;
- };
- };
- };
-
- gmac1: eth1@30250000 {
- compatible = "be,dwmac", "snps,dwmac-3.710", "snps,dwmac";
- reg = <0x0 0x30250000 0x0 0x10000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- max-speed = <1000>;
- clocks = <&soc_ethclk>, <&cmu0_xgbe 13>;
- clock-names = "stmmaceth", "tx2_clk";
- mac-address = [ 00 00 00 00 00 00 ];
- local-mac-address = [ 00 00 00 00 00 00 ];
- phy-mode = "rgmii-id";
- phy-handle = <&gmac1_phy>;
- snps,fixed-burst;
- snps,axi-config = <&axi_gmac>;
- snps,no-pbl-x8;
- snps,txpbl = <4>;
- snps,rxpbl = <4>;
- snps,reset-delays-us = <0 10200 1000>;
- status = "disabled";
- dma-coherent;
-
- gmdio1: gmac1_mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- gmac1_phy: ethernet-phy@3 {
- compatible = "ethernet-phy-id0022.1620", "ethernet-phy-ieee802.3-c22";
- reg = <0x3>;
- txd0-skew-ps = <0>;
- txd1-skew-ps = <0>;
- txd2-skew-ps = <0>;
- txd3-skew-ps = <0>;
- txc-skew-ps = <0xff>;
- };
- };
- };
-
- /* Baikal internal MDIO */
- mdio0: be-mdio {
- compatible = "be,mdio-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
- mdc-pin = <&porta 30 GPIO_ACTIVE_HIGH>;
- mdio-pin = <&porta 29 GPIO_ACTIVE_HIGH>;
- clocks = <&gpio_clk>;
- clock-names = "gpioclk";
-
- mv_ch0: ethernet-phy@c {
- compatible = "marvell,88x2222", "ethernet-phy-ieee802.3-c45";
- reg = <0x0c>;
- phy-mode = "xgmii";
- mv,line-mode = "KR";
- mv,host-mode = "KX4";
- };
-
- mv_ch2: ethernet-phy@e {
- compatible = "marvell,88x2222", "ethernet-phy-ieee802.3-c45";
- reg = <0x0e>;
- phy-mode = "xgmii";
- mv,line-mode = "KR";
- mv,host-mode = "KX4";
- };
- };
-
- /* XGMAC0 */
- xgmac0: eth2@30200000 {
- compatible = "amd,xgbe-seattle-v1a";
- reg = <0x0 0x30200000 0x0 0x10000>,
- <0x0 0x30210000 0x0 0x10000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
- fsl,num-rx-queues=<3>;
- clocks = <&soc_xgbeclk>, <&soc_xgbeclk>, <&soc_xgbeclk>;
- clock-names = "dma_clk", "ptp_clk", "xgbe_clk";
- phy-mode = "xgmii";
- mac-address = [ 00 20 13 ba 1c a1 ];
- local-mac-address = [ 00 20 13 ba 1c a1 ];
- be,pcs-mode = "KX4";
- ext-phy-handle = <&mv_ch0>;
- status = "disabled";
- amd,per-channel-interrupt;
- amd,speed-set = <0>;
- #stream-id-cells = <16>;
- };
-
- /* XGMAC1 */
- xgmac1: eth3@30220000 {
- compatible = "amd,xgbe-seattle-v1a";
- reg = <0x0 0x30220000 0x0 0x10000>,
- <0x0 0x30230000 0x0 0x10000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
- fsl,num-rx-queues=<3>;
- clocks = <&soc_xgbeclk>, <&soc_xgbeclk>, <&soc_xgbeclk>;
- clock-names = "dma_clk", "ptp_clk", "xgbe_clk";
- phy-mode = "xgmii";
- mac-address = [ 00 20 13 ba 1c a2 ];
- local-mac-address = [ 00 20 13 ba 1c a2 ];
- be,pcs-mode = "KX4";
- ext-phy-handle = <&mv_ch2>;
- status = "disabled";
- amd,per-channel-interrupt;
- amd,speed-set = <0>;
- #stream-id-cells = <16>;
- };
-
- /* HDMI VDU (30260000, 10000, SPI_361-362_?) */
- vdu1: vdu_hdmi@30260000 {
- compatible = "baikal,vdu";
- reg = <0x0 0x30260000 0x0 0x1000>;
- interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, /* VDU INTR */
- <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; /* VDU INTR_CDD */
- clocks = <&cmu1_xgbe 0>;
- clock-names = "pclk";
- status = "disabled";
-
- port {
- vdu_hdmi_out: endpoint {
- remote-endpoint = <&hdmi_tx_in>;
- };
- };
- };
-
- hdmi: hdmi@30280000 {
- compatible = "baikal,hdmi";
- reg = <0 0x30280000 0 0x20000>;
- reg-io-width = <4>;
- interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cmu0_xgbe 0>, <&cmu0_xgbe 17>;
- clock-names = "iahb", "isfr";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- hdmi_tx_in: endpoint {
- remote-endpoint = <&vdu_hdmi_out>;
- };
- };
- port@1 {
- reg = <1>;
- hdmi_tx_out: endpoint {
- remote-endpoint = <&hdmi_con>;
- };
- };
- };
- };
- }; /* end of soc node */
-
- hdmi-out {
- compatible = "hdmi-connector";
- label = "HDMI0 OUT";
- type = "a";
-
- port {
- hdmi_con: endpoint {
- remote-endpoint = <&hdmi_tx_out>;
- };
- };
- };
-};
--
2.33.3
^ permalink raw reply [flat|nested] 9+ messages in thread* [d-kernel] [PATCH vtry2 3/7] Added PCI-E driver for Baikal-M with SDK-M 5.5 firmware
2022-09-02 7:33 [d-kernel] (try2) sisyphus/std-def: Байкал-М: поддержка SDK-M 5.5, ноутбука Элпитех Alexey Sheplyakov
2022-09-02 7:33 ` [d-kernel] [PATCH vtry2 1/7] arm64: dts: wiped out obsolete Baikal-M device trees Alexey Sheplyakov
2022-09-02 7:33 ` [d-kernel] [PATCH vtry2 2/7] net: stmmac: removed obsolete Baikal-M specific mdio reset Alexey Sheplyakov
@ 2022-09-02 7:33 ` Alexey Sheplyakov
2022-09-02 7:33 ` [d-kernel] [PATCH vtry2 4/7] input: new driver - serdev-serio Alexey Sheplyakov
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Alexey Sheplyakov @ 2022-09-02 7:33 UTC (permalink / raw)
To: devel-kernel; +Cc: rst, nir, sin
This driver works with firmware from SDK-M 5.5. dw-pcie should be
used with older firmware (such as SDK-M 5.3)
Note: this driver uses `baikal,bm1000-pcie` as a compatible string.
Hence the kernel with this driver can run on Baikal-M boards with
older firmware (and use dw-pcie driver instead of this one).
Known to work with Delta Computers' Rhodeola board, firmware
5.5_rdl_220425_1_debug.cap
X-DONTUPSTREAM
X-feature-Baikal-M
Co-developed-by: Pavel Parkhomenko <pavel.parkhomenko@baikalelectronics.ru>
Co-developed-by: Mikhail Ivanov <michail.ivanov@baikalelectronics.ru>
Co-developed-by: Aleksandr Efimov <alexander.efimov@baikalelectronics.ru>
Signed-off-by: Alexey Sheplyakov <asheplyakov@basealt.ru>
---
drivers/pci/controller/dwc/Kconfig | 12 +
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pcie-baikal.c | 740 ++++++++++++++++++
.../pci/controller/dwc/pcie-designware-plat.c | 5 +
4 files changed, 758 insertions(+)
create mode 100644 drivers/pci/controller/dwc/pcie-baikal.c
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index 76c0a63a3f64..057acee76d2c 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -264,6 +264,18 @@ config PCIE_KEEMBAY_EP
The PCIe controller is based on DesignWare Hardware and uses
DesignWare core functions.
+config PCI_BAIKAL
+ bool "Baikal SoC PCIe controller"
+ depends on ARCH_BAIKAL
+ depends on OF && HAS_IOMEM
+ select PCIE_DW_HOST
+ select PCI_MSI_IRQ_DOMAIN
+ select PCI_QUIRKS if ACPI
+ help
+ Enables support for the PCIe controller in the Baikal SoC. There are
+ three instances of PCIe controller in Baikal-M. Two of the controllers
+ support PCIe 3.0 x4 and the remaining one supports PCIe 3.0 x8.
+
config PCIE_KIRIN
depends on OF && (ARM64 || COMPILE_TEST)
bool "HiSilicon Kirin series SoCs PCIe controllers"
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index 73244409792c..a9980d443a67 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o
obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
+obj-$(CONFIG_PCI_BAIKAL) += pcie-baikal.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pcie-baikal.c b/drivers/pci/controller/dwc/pcie-baikal.c
new file mode 100644
index 000000000000..375a10d7bf87
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-baikal.c
@@ -0,0 +1,740 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe RC driver for Baikal-M SoC
+ *
+ * Copyright (C) 2019-2021 Baikal Electronics, JSC
+ * Authors: Pavel Parkhomenko <pavel.parkhomenko@baikalelectronics.ru>
+ * Mikhail Ivanov <michail.ivanov@baikalelectronics.ru>
+ * Aleksandr Efimov <alexander.efimov@baikalelectronics.ru>
+ */
+
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/irqchip/arm-gic-v3.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/pci.h>
+#include <linux/pci-ecam.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/resource.h>
+
+#include "pcie-designware.h"
+
+struct baikal_pcie_rc {
+ struct dw_pcie *pcie;
+ unsigned num;
+ struct regmap *lcru;
+ struct gpio_desc *reset_gpio;
+ bool reset_active_low;
+ char reset_name[32];
+ bool retrained;
+};
+
+#define to_baikal_pcie_rc(x) dev_get_drvdata((x)->dev)
+
+#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_REG 0x78
+#define PCIE_CAP_CORR_ERR_REPORT_EN BIT(0)
+#define PCIE_CAP_NON_FATAL_ERR_REPORT_EN BIT(1)
+#define PCIE_CAP_FATAL_ERR_REPORT_EN BIT(2)
+#define PCIE_CAP_UNSUPPORT_REQ_REP_EN BIT(3)
+
+#define PCIE_LINK_CAPABILITIES_REG 0x7c
+
+#define PCIE_LINK_CONTROL_LINK_STATUS_REG 0x80
+#define PCIE_CAP_LINK_SPEED_MASK 0xf0000
+#define PCIE_CAP_LINK_SPEED_SHIFT 16
+#define PCIE_CAP_NEGO_LINK_WIDTH_MASK 0x3f00000
+#define PCIE_CAP_NEGO_LINK_WIDTH_SHIFT 20
+#define PCIE_CAP_LINK_TRAINING BIT(27)
+
+#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG 0x8c
+#define PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN BIT(0)
+#define PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN BIT(1)
+#define PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN BIT(2)
+#define PCIE_CAP_PME_INT_EN BIT(3)
+
+#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG 0xa0
+#define PCIE_CAP_TARGET_LINK_SPEED_MASK 0xf
+
+#define PCIE_UNCORR_ERR_STATUS_REG 0x104
+#define PCIE_CORR_ERR_STATUS_REG 0x110
+
+#define PCIE_ROOT_ERR_CMD_REG 0x12c
+#define PCIE_CORR_ERR_REPORTING_EN BIT(0)
+#define PCIE_NON_FATAL_ERR_REPORTING_EN BIT(1)
+#define PCIE_FATAL_ERR_REPORTING_EN BIT(2)
+
+#define PCIE_ROOT_ERR_STATUS_REG 0x130
+
+#define PCIE_GEN2_CTRL_REG 0x80c
+#define PCIE_DIRECT_SPEED_CHANGE BIT(17)
+
+#define PCIE_IATU_VIEWPORT_REG 0x900
+#define PCIE_IATU_REGION_OUTBOUND 0
+#define PCIE_IATU_REGION_CTRL_2_REG 0x908
+#define PCIE_IATU_REGION_CTRL_2_REG_SHIFT_MODE BIT(28)
+
+#define BAIKAL_LCRU_PCIE_RESET_BASE 0x50000
+#define BAIKAL_LCRU_PCIE_RESET(x) ((x * 0x20) + BAIKAL_LCRU_PCIE_RESET_BASE)
+#define BAIKAL_PCIE_PHY_RST BIT(0)
+#define BAIKAL_PCIE_PIPE_RST BIT(4) /* x4 controllers only */
+#define BAIKAL_PCIE_PIPE0_RST BIT(4) /* x8 controller only */
+#define BAIKAL_PCIE_PIPE1_RST BIT(5) /* x8 controller only */
+#define BAIKAL_PCIE_CORE_RST BIT(8)
+#define BAIKAL_PCIE_PWR_RST BIT(9)
+#define BAIKAL_PCIE_STICKY_RST BIT(10)
+#define BAIKAL_PCIE_NONSTICKY_RST BIT(11)
+#define BAIKAL_PCIE_HOT_RST BIT(12)
+#define BAIKAL_PCIE_ADB_PWRDWN BIT(13)
+
+#define BAIKAL_LCRU_PCIE_STATUS_BASE 0x50004
+#define BAIKAL_LCRU_PCIE_STATUS(x) ((x * 0x20) + BAIKAL_LCRU_PCIE_STATUS_BASE)
+#define BAIKAL_PCIE_LTSSM_MASK 0x3f
+#define BAIKAL_PCIE_LTSSM_STATE_L0 0x11
+
+#define BAIKAL_LCRU_PCIE_GEN_CTL_BASE 0x50008
+#define BAIKAL_LCRU_PCIE_GEN_CTL(x) ((x * 0x20) + BAIKAL_LCRU_PCIE_GEN_CTL_BASE)
+#define BAIKAL_PCIE_LTSSM_ENABLE BIT(1)
+#define BAIKAL_PCIE_DBI2_MODE BIT(2)
+#define BAIKAL_PCIE_PHY_MGMT_ENABLE BIT(3)
+
+#define BAIKAL_LCRU_PCIE_MSI_TRANS_CTL2 0x500f8
+#define BAIKAL_LCRU_PCIE_MSI_TRANS_CTL2_PCIE_MSI_TRANS_EN(x) BIT(9 + (x))
+#define BAIKAL_LCRU_PCIE_MSI_TRANS_CTL2_PCIE_RCNUM(x) ((x) << (2 * (x)))
+#define BAIKAL_LCRU_PCIE_MSI_TRANS_CTL2_PCIE_RCNUM_MASK(x) ((3) << (2 * (x)))
+
+static int baikal_pcie_link_up(struct dw_pcie *pcie)
+{
+ struct baikal_pcie_rc *rc = to_baikal_pcie_rc(pcie);
+ u32 reg;
+
+ regmap_read(rc->lcru, BAIKAL_LCRU_PCIE_GEN_CTL(rc->num), ®);
+ if (!(reg & BAIKAL_PCIE_LTSSM_ENABLE)) {
+ return 0;
+ }
+
+ regmap_read(rc->lcru, BAIKAL_LCRU_PCIE_STATUS(rc->num), ®);
+ return (reg & BAIKAL_PCIE_LTSSM_MASK) == BAIKAL_PCIE_LTSSM_STATE_L0;
+}
+
+static int baikal_pcie_host_init(struct pcie_port *pp)
+{
+ struct dw_pcie *pcie = to_dw_pcie_from_pp(pp);
+ struct baikal_pcie_rc *rc = to_baikal_pcie_rc(pcie);
+ struct device *dev = pcie->dev;
+ int err;
+ int linkup;
+ unsigned idx;
+ u32 reg;
+
+ /* Disable access to PHY registers and DBI2 mode */
+ regmap_read(rc->lcru, BAIKAL_LCRU_PCIE_GEN_CTL(rc->num), ®);
+ reg &= ~(BAIKAL_PCIE_PHY_MGMT_ENABLE |
+ BAIKAL_PCIE_DBI2_MODE);
+ regmap_write(rc->lcru, BAIKAL_LCRU_PCIE_GEN_CTL(rc->num), reg);
+
+ rc->retrained = false;
+ linkup = baikal_pcie_link_up(pcie);
+
+ /* If link is not established yet, reset the RC */
+ if (!linkup) {
+ /* Disable link training */
+ regmap_read(rc->lcru, BAIKAL_LCRU_PCIE_GEN_CTL(rc->num), ®);
+ reg &= ~BAIKAL_PCIE_LTSSM_ENABLE;
+ regmap_write(rc->lcru, BAIKAL_LCRU_PCIE_GEN_CTL(rc->num), reg);
+
+ /* Assert PERST pin */
+ if (rc->reset_gpio != NULL) {
+ unsigned long gpio_flags;
+
+ if (rc->reset_active_low) {
+ gpio_flags = GPIOF_ACTIVE_LOW |
+ GPIOF_OUT_INIT_LOW;
+ } else {
+ gpio_flags = GPIOF_OUT_INIT_HIGH;
+ }
+
+ err = devm_gpio_request_one(dev,
+ desc_to_gpio(rc->reset_gpio),
+ gpio_flags, rc->reset_name);
+ if (err) {
+ dev_err(dev, "request GPIO failed (%d)\n", err);
+ return err;
+ }
+ }
+
+ /* Reset the RC */
+ regmap_read(rc->lcru, BAIKAL_LCRU_PCIE_RESET(rc->num), ®);
+ reg |= BAIKAL_PCIE_NONSTICKY_RST |
+ BAIKAL_PCIE_STICKY_RST |
+ BAIKAL_PCIE_PWR_RST |
+ BAIKAL_PCIE_CORE_RST |
+ BAIKAL_PCIE_PHY_RST;
+
+ /* If the RC is PCIe x8, reset PIPE0 and PIPE1 */
+ if (rc->num == 2) {
+ reg |= BAIKAL_PCIE_PIPE0_RST |
+ BAIKAL_PCIE_PIPE1_RST;
+ } else {
+ reg |= BAIKAL_PCIE_PIPE_RST;
+ }
+
+ regmap_write(rc->lcru, BAIKAL_LCRU_PCIE_RESET(rc->num), reg);
+
+ usleep_range(20000, 30000);
+
+ if (rc->reset_gpio != NULL) {
+ /* Deassert PERST pin */
+ gpiod_set_value_cansleep(rc->reset_gpio, 0);
+ }
+
+ /* Deassert PHY reset */
+ regmap_read(rc->lcru, BAIKAL_LCRU_PCIE_RESET(rc->num), ®);
+ reg &= ~BAIKAL_PCIE_PHY_RST;
+ regmap_write(rc->lcru, BAIKAL_LCRU_PCIE_RESET(rc->num), reg);
+
+ /* Deassert all software controlled resets */
+ regmap_read(rc->lcru, BAIKAL_LCRU_PCIE_RESET(rc->num), ®);
+ reg &= ~(BAIKAL_PCIE_ADB_PWRDWN |
+ BAIKAL_PCIE_HOT_RST |
+ BAIKAL_PCIE_NONSTICKY_RST |
+ BAIKAL_PCIE_STICKY_RST |
+ BAIKAL_PCIE_PWR_RST |
+ BAIKAL_PCIE_CORE_RST |
+ BAIKAL_PCIE_PHY_RST);
+
+ if (rc->num == 2) {
+ reg &= ~(BAIKAL_PCIE_PIPE0_RST |
+ BAIKAL_PCIE_PIPE1_RST);
+ } else {
+ reg &= ~BAIKAL_PCIE_PIPE_RST;
+ }
+
+ regmap_write(rc->lcru, BAIKAL_LCRU_PCIE_RESET(rc->num), reg);
+ }
+
+ /* Deinitialise all iATU regions */
+ for (idx = 0; idx < pcie->num_ob_windows; ++idx) {
+ dw_pcie_writel_dbi(pcie, PCIE_IATU_VIEWPORT_REG,
+ PCIE_IATU_REGION_OUTBOUND | idx);
+ dw_pcie_writel_dbi(pcie, PCIE_IATU_REGION_CTRL_2_REG, 0);
+ }
+
+ dw_pcie_setup_rc(pp);
+
+ /* Set prog-if 01 [subtractive decode] */
+ dw_pcie_dbi_ro_wr_en(pcie);
+ reg = dw_pcie_readl_dbi(pcie, PCI_CLASS_REVISION);
+ reg = (reg & 0xffff00ff) | (1 << 8);
+ dw_pcie_writel_dbi(pcie, PCI_CLASS_REVISION, reg);
+ dw_pcie_dbi_ro_wr_dis(pcie);
+
+ /* Enable error reporting */
+ reg = dw_pcie_readl_dbi(pcie, PCIE_ROOT_ERR_CMD_REG);
+ reg |= PCIE_CORR_ERR_REPORTING_EN |
+ PCIE_NON_FATAL_ERR_REPORTING_EN |
+ PCIE_FATAL_ERR_REPORTING_EN;
+ dw_pcie_writel_dbi(pcie, PCIE_ROOT_ERR_CMD_REG, reg);
+
+ reg = dw_pcie_readl_dbi(pcie, PCIE_DEVICE_CONTROL_DEVICE_STATUS_REG);
+ reg |= PCIE_CAP_CORR_ERR_REPORT_EN |
+ PCIE_CAP_NON_FATAL_ERR_REPORT_EN |
+ PCIE_CAP_FATAL_ERR_REPORT_EN |
+ PCIE_CAP_UNSUPPORT_REQ_REP_EN;
+ dw_pcie_writel_dbi(pcie, PCIE_DEVICE_CONTROL_DEVICE_STATUS_REG, reg);
+
+ reg = dw_pcie_readl_dbi(pcie, PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG);
+ reg |= PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN |
+ PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN |
+ PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN |
+ PCIE_CAP_PME_INT_EN;
+ dw_pcie_writel_dbi(pcie, PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG, reg);
+
+ if (linkup) {
+ dev_info(dev, "link is already up\n");
+ } else {
+ /* Use Gen1 mode for link establishing */
+ reg = dw_pcie_readl_dbi(pcie,
+ PCIE_LINK_CONTROL2_LINK_STATUS2_REG);
+ reg &= ~PCIE_CAP_TARGET_LINK_SPEED_MASK;
+ reg |= 1;
+ dw_pcie_writel_dbi(pcie,
+ PCIE_LINK_CONTROL2_LINK_STATUS2_REG, reg);
+
+ /*
+ * Clear DIRECT_SPEED_CHANGE bit. It has been set by
+ * dw_pcie_setup_rc(pp). This bit causes link retraining. But
+ * link retraining should be performed later by calling the
+ * baikal_pcie_link_speed_fixup().
+ */
+ reg = dw_pcie_readl_dbi(pcie, PCIE_GEN2_CTRL_REG);
+ reg &= ~PCIE_DIRECT_SPEED_CHANGE;
+ dw_pcie_writel_dbi(pcie, PCIE_GEN2_CTRL_REG, reg);
+
+ /* Establish link */
+ regmap_read(rc->lcru, BAIKAL_LCRU_PCIE_GEN_CTL(rc->num), ®);
+ reg |= BAIKAL_PCIE_LTSSM_ENABLE;
+ regmap_write(rc->lcru, BAIKAL_LCRU_PCIE_GEN_CTL(rc->num), reg);
+
+ dw_pcie_wait_for_link(pcie);
+ }
+
+ regmap_read(rc->lcru, BAIKAL_LCRU_PCIE_MSI_TRANS_CTL2, ®);
+ reg &= ~BAIKAL_LCRU_PCIE_MSI_TRANS_CTL2_PCIE_RCNUM_MASK(rc->num);
+ reg |= BAIKAL_LCRU_PCIE_MSI_TRANS_CTL2_PCIE_RCNUM(rc->num);
+ reg |= BAIKAL_LCRU_PCIE_MSI_TRANS_CTL2_PCIE_MSI_TRANS_EN(rc->num);
+ regmap_write(rc->lcru, BAIKAL_LCRU_PCIE_MSI_TRANS_CTL2, reg);
+
+ return 0;
+}
+
+static const struct dw_pcie_host_ops baikal_pcie_host_ops = {
+ .host_init = baikal_pcie_host_init
+};
+
+static void baikal_pcie_link_print_status(struct baikal_pcie_rc *rc)
+{
+ struct dw_pcie *pcie = rc->pcie;
+ struct device *dev = pcie->dev;
+ u32 reg;
+ unsigned speed, width;
+
+ if (!baikal_pcie_link_up(pcie)) {
+ dev_info(dev, "link is down\n");
+ return;
+ }
+
+ reg = dw_pcie_readl_dbi(pcie, PCIE_LINK_CONTROL_LINK_STATUS_REG);
+ speed = (reg & PCIE_CAP_LINK_SPEED_MASK) >> PCIE_CAP_LINK_SPEED_SHIFT;
+ width = (reg & PCIE_CAP_NEGO_LINK_WIDTH_MASK) >>
+ PCIE_CAP_NEGO_LINK_WIDTH_SHIFT;
+
+ dev_info(dev, "link status is Gen%u%s, x%u\n", speed,
+ reg & PCIE_CAP_LINK_TRAINING ? " (training)" : "", width);
+}
+
+static unsigned baikal_pcie_link_is_training(struct baikal_pcie_rc *rc)
+{
+ struct dw_pcie *pcie = rc->pcie;
+ return dw_pcie_readl_dbi(pcie, PCIE_LINK_CONTROL_LINK_STATUS_REG) &
+ PCIE_CAP_LINK_TRAINING;
+}
+
+static bool baikal_pcie_link_wait_training_done(struct baikal_pcie_rc *rc)
+{
+ struct dw_pcie *pcie = rc->pcie;
+ struct device *dev = pcie->dev;
+ unsigned long start_jiffies = jiffies;
+
+ while (baikal_pcie_link_is_training(rc)) {
+ if (time_after(jiffies, start_jiffies + HZ)) {
+ dev_err(dev, "link training timeout occured\n");
+ return false;
+ }
+ udelay(100);
+ }
+ return true;
+}
+
+static void baikal_pcie_link_retrain(struct baikal_pcie_rc *rc,
+ int target_speed)
+{
+ struct dw_pcie *pcie = rc->pcie;
+ struct device *dev = pcie->dev;
+ u32 reg;
+ unsigned long start_jiffies;
+
+ dev_info(dev, "retrain link to Gen%u\n", target_speed);
+
+ /* In case link is already training wait for training to complete */
+ baikal_pcie_link_wait_training_done(rc);
+
+ /* Set desired speed */
+ reg = dw_pcie_readl_dbi(pcie, PCIE_LINK_CONTROL2_LINK_STATUS2_REG);
+ reg &= ~PCIE_CAP_TARGET_LINK_SPEED_MASK;
+ reg |= target_speed;
+ dw_pcie_writel_dbi(pcie, PCIE_LINK_CONTROL2_LINK_STATUS2_REG, reg);
+
+ /* Deassert and assert DIRECT_SPEED_CHANGE bit */
+ reg = dw_pcie_readl_dbi(pcie, PCIE_GEN2_CTRL_REG);
+ reg &= ~PCIE_DIRECT_SPEED_CHANGE;
+ dw_pcie_writel_dbi(pcie, PCIE_GEN2_CTRL_REG, reg);
+ reg |= PCIE_DIRECT_SPEED_CHANGE;
+ dw_pcie_writel_dbi(pcie, PCIE_GEN2_CTRL_REG, reg);
+
+ /* Wait for link training begin */
+ start_jiffies = jiffies;
+ while (!baikal_pcie_link_is_training(rc)) {
+ if (time_after(jiffies, start_jiffies + HZ)) {
+ dev_err(dev, "link training has not started\n");
+ /* Don't wait for training_done() if it hasn't started */
+ return;
+ }
+ udelay(100);
+ }
+
+ /* Wait for link training end */
+ if (!baikal_pcie_link_wait_training_done(rc)) {
+ return;
+ }
+
+ if (!dw_pcie_wait_for_link(pcie)) {
+ /* Wait if link has switched to configuration/recovery state */
+ baikal_pcie_link_wait_training_done(rc);
+ baikal_pcie_link_print_status(rc);
+ }
+}
+
+static void baikal_pcie_link_speed_fixup(struct pci_dev *pdev)
+{
+ struct pcie_port *pp = pdev->bus->sysdata;
+ struct dw_pcie *pcie = to_dw_pcie_from_pp(pp);
+ struct baikal_pcie_rc *rc = to_baikal_pcie_rc(pcie);
+ unsigned dev_lnkcap_speed;
+ unsigned dev_lnkcap_width;
+ unsigned rc_lnkcap_speed;
+ unsigned rc_lnksta_speed;
+ unsigned rc_target_speed;
+ u32 reg;
+
+ /* Skip Root Bridge */
+ if (!pdev->bus->self) {
+ return;
+ }
+
+ /* Skip any devices not directly connected to the RC */
+ if (pdev->bus->self->bus->number != pp->bridge->bus->number) {
+ return;
+ }
+
+ /* Skip if the bus has already been retrained */
+ if (rc->retrained) {
+ return;
+ }
+
+ reg = dw_pcie_readl_dbi(pcie, PCIE_LINK_CAPABILITIES_REG);
+ rc_lnkcap_speed = reg & PCI_EXP_LNKCAP_SLS;
+
+ reg = dw_pcie_readl_dbi(pcie, PCIE_LINK_CONTROL_LINK_STATUS_REG);
+ rc_lnksta_speed = (reg & PCIE_CAP_LINK_SPEED_MASK) >>
+ PCIE_CAP_LINK_SPEED_SHIFT;
+
+ pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®);
+ dev_lnkcap_speed = (reg & PCI_EXP_LNKCAP_SLS);
+ dev_lnkcap_width = (reg & PCI_EXP_LNKCAP_MLW) >>
+ PCI_EXP_LNKSTA_NLW_SHIFT;
+
+ baikal_pcie_link_print_status(rc);
+ dev_info(&pdev->dev, "device link capability is Gen%u, x%u\n",
+ dev_lnkcap_speed, dev_lnkcap_width);
+
+ /*
+ * Gen1->Gen3 is suitable way of retraining.
+ * Gen1->Gen2 is used when Gen3 could not be reached.
+ * Gen2->Gen3 causes system freezing sometimes.
+ */
+ if (rc_lnkcap_speed < dev_lnkcap_speed) {
+ rc_target_speed = rc_lnkcap_speed;
+ } else {
+ rc_target_speed = dev_lnkcap_speed;
+ }
+
+ while (rc_lnksta_speed < rc_target_speed) {
+ /* Try to change link speed */
+ baikal_pcie_link_retrain(rc, rc_target_speed);
+
+ /* Check if the link is down after retrain */
+ if (!baikal_pcie_link_up(pcie)) {
+ /*
+ * Check if the link has already been down and
+ * the link is not re-established at Gen1.
+ */
+ if (rc_lnksta_speed == 0 && rc_target_speed == 1) {
+ /* Unable to re-establish the link */
+ break;
+ }
+
+ rc_lnksta_speed = 0;
+ if (rc_target_speed > 1) {
+ /* Try to use lower speed */
+ --rc_target_speed;
+ }
+
+ continue;
+ }
+
+ reg = dw_pcie_readl_dbi(pcie,
+ PCIE_LINK_CONTROL_LINK_STATUS_REG);
+ rc_lnksta_speed = (reg & PCIE_CAP_LINK_SPEED_MASK) >>
+ PCIE_CAP_LINK_SPEED_SHIFT;
+ /* Check if the targeted speed has not been reached */
+ if (rc_lnksta_speed < rc_target_speed && rc_target_speed > 1) {
+ /* Try to use lower speed */
+ --rc_target_speed;
+ }
+ }
+
+ rc->retrained = true;
+}
+
+static void baikal_pcie_link_retrain_bus(const struct pci_bus *bus)
+{
+ struct pci_dev *dev;
+
+ list_for_each_entry(dev, &bus->devices, bus_list) {
+ baikal_pcie_link_speed_fixup(dev);
+ }
+
+ list_for_each_entry(dev, &bus->devices, bus_list) {
+ if (dev->subordinate) {
+ baikal_pcie_link_retrain_bus(dev->subordinate);
+ }
+ }
+}
+
+static irqreturn_t baikal_pcie_aer_irq_handler(int irq, void *arg)
+{
+ struct baikal_pcie_rc *rc = arg;
+ struct dw_pcie *pcie = rc->pcie;
+ struct device *dev = pcie->dev;
+ u32 corr_err_status;
+ u32 dev_ctrl_dev_status;
+ u32 root_err_status;
+ u32 uncorr_err_status;
+
+ uncorr_err_status = dw_pcie_readl_dbi(pcie,
+ PCIE_UNCORR_ERR_STATUS_REG);
+ corr_err_status = dw_pcie_readl_dbi(pcie,
+ PCIE_CORR_ERR_STATUS_REG);
+ root_err_status = dw_pcie_readl_dbi(pcie,
+ PCIE_ROOT_ERR_STATUS_REG);
+ dev_ctrl_dev_status = dw_pcie_readl_dbi(pcie,
+ PCIE_DEVICE_CONTROL_DEVICE_STATUS_REG);
+ dev_err(dev,
+ "dev_err:0x%x root_err:0x%x uncorr_err:0x%x corr_err:0x%x\n",
+ (dev_ctrl_dev_status & 0xf0000) >> 16,
+ root_err_status, uncorr_err_status, corr_err_status);
+
+ dw_pcie_writel_dbi(pcie,
+ PCIE_UNCORR_ERR_STATUS_REG, uncorr_err_status);
+ dw_pcie_writel_dbi(pcie,
+ PCIE_CORR_ERR_STATUS_REG, corr_err_status);
+ dw_pcie_writel_dbi(pcie,
+ PCIE_ROOT_ERR_STATUS_REG, root_err_status);
+ dw_pcie_writel_dbi(pcie,
+ PCIE_DEVICE_CONTROL_DEVICE_STATUS_REG, dev_ctrl_dev_status);
+
+ return IRQ_HANDLED;
+}
+
+static int baikal_pcie_add_pcie_port(struct baikal_pcie_rc *rc,
+ struct platform_device *pdev)
+{
+ struct dw_pcie *pcie = rc->pcie;
+ struct pcie_port *pp = &pcie->pp;
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ pp->irq = platform_get_irq(pdev, 0);
+ if (pp->irq < 0) {
+ return pp->irq;
+ }
+
+ ret = devm_request_irq(dev, pp->irq, baikal_pcie_aer_irq_handler,
+ IRQF_SHARED, "bm1000-pcie-aer", rc);
+
+ if (ret) {
+ dev_err(dev, "failed to request irq %d\n", pp->irq);
+ return ret;
+ }
+
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
+ pp->msi_irq = platform_get_irq(pdev, 1);
+ if (pp->msi_irq < 0) {
+ return pp->msi_irq;
+ }
+ }
+
+ pp->ops = &baikal_pcie_host_ops;
+
+ ret = dw_pcie_host_init(pp);
+ if (ret) {
+ dev_err(dev, "Failed to initialize host\n");
+ return ret;
+ }
+
+ baikal_pcie_link_retrain_bus(pp->bridge->bus);
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int baikal_pcie_pm_resume(struct device *dev)
+{
+ struct baikal_pcie_rc *rc = dev_get_drvdata(dev);
+ struct dw_pcie *pcie = rc->pcie;
+ u32 reg;
+
+ /* Set Memory Space Enable (MSE) bit */
+ reg = dw_pcie_readl_dbi(pcie, PCI_COMMAND);
+ reg |= PCI_COMMAND_MEMORY;
+ dw_pcie_writel_dbi(pcie, PCI_COMMAND, reg);
+ return 0;
+}
+
+static int baikal_pcie_pm_resume_noirq(struct device *dev)
+{
+ return 0;
+}
+
+static int baikal_pcie_pm_suspend(struct device *dev)
+{
+ struct baikal_pcie_rc *rc = dev_get_drvdata(dev);
+ struct dw_pcie *pcie = rc->pcie;
+ u32 reg;
+
+ /* Clear Memory Space Enable (MSE) bit */
+ reg = dw_pcie_readl_dbi(pcie, PCI_COMMAND);
+ reg &= ~PCI_COMMAND_MEMORY;
+ dw_pcie_writel_dbi(pcie, PCI_COMMAND, reg);
+ return 0;
+}
+
+static int baikal_pcie_pm_suspend_noirq(struct device *dev)
+{
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops baikal_pcie_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(baikal_pcie_pm_suspend,
+ baikal_pcie_pm_resume)
+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(baikal_pcie_pm_suspend_noirq,
+ baikal_pcie_pm_resume_noirq)
+};
+
+static const struct of_device_id of_baikal_pcie_match[] = {
+ { .compatible = "baikal,bm1000-pcie" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, of_baikal_pcie_match);
+
+static const struct dw_pcie_ops baikal_pcie_ops = {
+ .link_up = baikal_pcie_link_up
+};
+
+static int baikal_pcie_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct baikal_pcie_rc *rc;
+ struct dw_pcie *pcie;
+ int ret;
+ u32 idx[2];
+ enum of_gpio_flags gpio_flags;
+ int reset_gpio;
+ struct resource *res;
+
+ if (!of_match_device(of_baikal_pcie_match, dev)) {
+ dev_err(dev, "device can't be handled by pcie-baikal\n");
+ return -EINVAL;
+ }
+
+ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
+ if (!pcie) {
+ return -ENOMEM;
+ }
+
+ pcie->dev = dev;
+ pcie->ops = &baikal_pcie_ops;
+
+ rc = devm_kzalloc(dev, sizeof(*rc), GFP_KERNEL);
+ if (!rc) {
+ return -ENOMEM;
+ }
+
+ rc->pcie = pcie;
+ rc->lcru = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "baikal,pcie-lcru");
+ if (IS_ERR(rc->lcru)) {
+ dev_err(dev, "No LCRU phandle specified\n");
+ rc->lcru = NULL;
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32_array(dev->of_node, "baikal,pcie-lcru", idx, 2)) {
+ dev_err(dev, "failed to read LCRU\n");
+ rc->lcru = NULL;
+ return -EINVAL;
+ }
+
+ if (idx[1] > 2) {
+ dev_err(dev, "incorrect pcie-lcru index\n");
+ rc->lcru = NULL;
+ return -EINVAL;
+ }
+
+ rc->num = idx[1];
+ reset_gpio = of_get_named_gpio_flags(dev->of_node, "reset-gpios", 0,
+ &gpio_flags);
+ if (gpio_is_valid(reset_gpio)) {
+ rc->reset_gpio = gpio_to_desc(reset_gpio);
+ rc->reset_active_low = !!(gpio_flags & OF_GPIO_ACTIVE_LOW);
+ snprintf(rc->reset_name, sizeof(rc->reset_name), "pcie%u-reset",
+ rc->num);
+ } else {
+ rc->reset_gpio = NULL;
+ }
+
+ pm_runtime_enable(dev);
+ ret = pm_runtime_get_sync(dev);
+ if (ret < 0) {
+ dev_err(dev, "pm_runtime_get_sync failed\n");
+ goto err_pm_disable;
+ }
+
+ platform_set_drvdata(pdev, rc);
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
+ if (res) {
+ devm_request_resource(dev, &iomem_resource, res);
+ pcie->dbi_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(pcie->dbi_base)) {
+ dev_err(dev, "error with ioremap\n");
+ ret = PTR_ERR(pcie->dbi_base);
+ goto err_pm_put;
+ }
+ } else {
+ dev_err(dev, "missing *dbi* reg space\n");
+ ret = -EINVAL;
+ goto err_pm_put;
+ }
+
+ ret = baikal_pcie_add_pcie_port(rc, pdev);
+ if (ret < 0) {
+ goto err_pm_put;
+ }
+
+ return 0;
+
+err_pm_put:
+ pm_runtime_put(dev);
+err_pm_disable:
+ pm_runtime_disable(dev);
+ return ret;
+}
+
+static struct platform_driver baikal_pcie_driver = {
+ .driver = {
+ .name = "baikal-pcie",
+ .of_match_table = of_baikal_pcie_match,
+ .suppress_bind_attrs = true,
+ .pm = &baikal_pcie_pm_ops
+ },
+ .probe = baikal_pcie_probe
+};
+
+module_platform_driver(baikal_pcie_driver);
+MODULE_DESCRIPTION("Baikal PCIe host controller driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
index 8851eb161a0e..a228655e4412 100644
--- a/drivers/pci/controller/dwc/pcie-designware-plat.c
+++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
@@ -126,6 +126,11 @@ static int dw_plat_pcie_probe(struct platform_device *pdev)
const struct dw_plat_pcie_of_data *data;
enum dw_pcie_device_mode mode;
+ if (of_device_is_compatible(dev->of_node, "baikal,bm1000-pcie")) {
+ dev_err(dev, "refusing to load on Baikal-M with SDK-M 5.{4,5}\n");
+ return -ENODEV;
+ }
+
match = of_match_device(dw_plat_pcie_of_match, dev);
if (!match)
return -EINVAL;
--
2.33.3
^ permalink raw reply [flat|nested] 9+ messages in thread