From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Thu, 27 Jan 2005 16:47:52 +0200 From: Alex Yustasov To: devel-kernel@altlinux.ru, lakostis@altlinux.ru Message-ID: <20050127144752.GA7697@server.by> Mail-Followup-To: Alex Yustasov , devel-kernel@altlinux.ru, lakostis@altlinux.ru Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="sm4nu43k4a2Rpi4c" Content-Disposition: inline User-Agent: Mutt/1.5.6+cvs20050115i Content-Transfer-Encoding: 7bit X-Antivirus-Scanner: Clean mail though you should still use an Antivirus X-Spam-Score: 0.0 (/) Cc: Subject: [d-kernel] =?koi8-r?b?8NLP?= wks26 X-BeenThere: devel-kernel@altlinux.ru X-Mailman-Version: 2.1.5 Precedence: list Reply-To: ALT Linux kernel packages development List-Id: ALT Linux kernel packages development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 27 Jan 2005 14:49:20 -0000 Archived-At: List-Archive: List-Post: --sm4nu43k4a2Rpi4c Content-Type: text/plain; charset=koi8-r Content-Disposition: inline Content-Transfer-Encoding: quoted-printable =FA=C4=D2=C1=D7=D3=D4=D7=D5=CA=D4=C5. =F5 =CD=C5=CE=D1 wks26 =D0=C1=C4=C1=CC=CF =D0=D2=C9 resume. =F7=C9=CE=CF=D7= =C1=D4 =C2=D9=CC 2.6_98_sched-fix-scheduling-latencies-in-mttrc.patch =C9=DA lowlatency. =F1 =C5=C7=CF =D0=CF=CD=C5=CE=D1=CC =CE=C5=CD=CE=CF=D6=CE=CF. =F7=CD=C5=D3= =D4=CF spin_lock_irq =C9 spin_unclock_irq =D0=CF=D3=D4=C1=D7=C9=CC spin_lock_irqsave =C9 spin_unlock_irqrestore. (=D7= =C1=D4=D4=C1=DE=C5) =F3 =CE=C9=CD =D2=C1=C2=CF=D4=C1=C5=D4. =FA=C1=CC=C9=D7=C1=D4=D8 =D7 cvs? --sm4nu43k4a2Rpi4c Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename="2.6_98_sched-fix-scheduling-latencies-in-mttrc.patch" diff -puN arch/i386/kernel/cpu/mtrr/generic.c~sched-fix-scheduling-latencies-in-mttrc arch/i386/kernel/cpu/mtrr/generic.c --- 25/arch/i386/kernel/cpu/mtrr/generic.c~sched-fix-scheduling-latencies-in-mttrc Tue Sep 14 17:42:08 2004 +++ 25-akpm/arch/i386/kernel/cpu/mtrr/generic.c Tue Sep 14 17:42:08 2004 @@ -240,11 +240,9 @@ /* Note that this is not ideal, since the cache is only flushed/disabled for this CPU while the MTRRs are changed, but changing this requires more invasive changes to the way the kernel boots */ - spin_lock(&set_atomicity_lock); /* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */ cr0 = read_cr0() | 0x40000000; /* set CD flag */ - wbinvd(); write_cr0(cr0); wbinvd(); @@ -266,8 +264,7 @@ static void post_set(void) { - /* Flush caches and TLBs */ - wbinvd(); + /* Flush TLBs (no need to flush caches - they are disabled) */ __flush_tlb(); /* Intel (P6) standard MTRRs */ @@ -279,12 +276,17 @@ /* Restore value of CR4 */ if ( cpu_has_pge ) write_cr4(cr4); - spin_unlock(&set_atomicity_lock); } static void generic_set_all(void) { - unsigned long mask, count; + unsigned long mask, count, flags; + + /* + * Since we are disabling the cache dont allow any interrupts - they + * would run extremely slow and would only increase the pain: + */ + spin_lock_irqsave(&set_atomicity_lock, flags); prepare_set(); @@ -293,6 +295,8 @@ post_set(); + spin_unlock_irqrestore(&set_atomicity_lock, flags); + /* Use the atomic bitops to update the global mask */ for (count = 0; count < sizeof mask * 8; ++count) { if (mask & 0x01) --sm4nu43k4a2Rpi4c--